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Forum Post: RE: DAC37J84: LVDS driving SYSREF input

I am trying to determine if I can AC couple LVDS. By the datasheet the part needs typical 400mV swing each leg (=800mVpp DIFF), and and minimum 200mV swing each leg (=400mVpp DIFF). So 320mV LVDS...

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Forum Post: RE: DAC539G2-Q1: SMART-DAC-EVM-GUI Error in VI at startup in...

Hi Adam, Does the FT4222 device show up as a device in device manager? When all other suggestions you have already found have failed, it seems to be a driver level issue that I have not been able to...

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Forum Post: RE: DAC539G2-Q1: SMART-DAC-EVM-GUI Error in VI at startup in...

In addition, I do know other engineers at your company have been able to use this GUI, so I do not think it is a firewall issue unless there is some difference between your two sites. Best, Katlynne

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Forum Post: RE: LM61495-Q1: About the Standard Label

Hello I will speak with our product engineers and get back to you as soon as possible. Thanks

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Forum Post: RE: DAC37J84: LVDS driving SYSREF input

Hi David, Yes, that should be fine. You can AC couple the LVDS. But you need to have a 100ohm diff term at the RX side, before the 0.1uF caps. Regards, Rob

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Forum Post: RE: ADS8598H: ADS8598H isolated interface to microcontroller

This looks good to me! Please do let us know how everything works out once you have your hardware together.

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Forum Post: RE: ADS1247: START and SYNC Commands

Hi George Sarkees, The behavior as described in the datasheet is what I am seeing on the EVM - see below (the REFOUT waveforms are not great because my logic analyzer has fairly low resolution analog,...

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Forum Post: RE: ADS1261: Responding with All Zeros

I just finished the additional tests. If all I do is pull the START pin high I do not see a 50 Hz signal on DRDY or any periodic waveform on it at all. The attached logic analyzer capture is our...

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Forum Post: RE: ADS125H01: ADS125H01

Hi paul brosens, I tried this on my EVM: setting the data rate to 5 SPS, FIR filter, internal clock, internal VREF, and grounding AIN0 and AIN1. Below is the data I got This matches very closely to...

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Forum Post: RE: ADS1261: Responding with All Zeros

Hi Everett Everett, Now SCLK is idling high, which will not work at all. SCLK needs to idle low, and you need to capture data on the falling edge of SCLK. You previously had the SCLK polarity correct...

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Forum Post: RE: ADS1261: Responding with All Zeros

OK, I will fix the clock back to what it was. Clock idle low, innactive outside word and capture falling edge. We have the logic analyzer connected to the 1261 DOUT/DRDY pin, the combined pin. I was...

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Forum Post: RE: ADS1261: Responding with All Zeros

Hi Everett Everett, Understood, we will wait for the results of your tests -Bryan

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Forum Post: RE: ADS1235: Inconsistent Measurement Drift and Step Changes in...

Hi Edgar Ripoll Vercellone, How are you exciting the bridge - voltage or current? What is the magnitude of the excitation voltage / current? Can you include a schematic? Are you using the AC...

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Forum Post: RE: ADS131M06: ADS131M06

We continue to try to make this work. You can see the logic analyzer is working in the 4 X 24 clock plot. The uC is correctly reading the values so SPI works. DRDY always goes high after 3X24 clocks....

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Forum Post: RE: ADS131M06: ADS131M06

Hi peter mccormick, What data rate are you operating at? Are you just powering up the ADC and sending data, such that all registers are at the default values? And what is the ADC clock speed that you...

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Forum Post: RE: ADC3562: Regarding register settings for ADC3562

Hi Oda, Thanks for your patience. I would review the datasheet and your prototype and come back if there are any specific issues or questions. Regards, Rob

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Forum Post: RE: DAC121S101-SEP: Peak solder temperature of DAC121S101WGMPR

Hi Arumuga, Please see the link for TI's recommendations on reflow. Let me know if this doesn't answer your question. Hermetic Package Reflow Profiles, Termination Finishes, and Lead Trim and Form...

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Forum Post: RE: ADS1148: Compliance voltage of IDAC Pin

Thanks for your supply. However, it seems to be no curve indicated IDAC voltage compliance @250uA in Figure 10. It should be the color the same as Figure 9? The IDAC voltage compliance seems increase...

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Forum Post: RE: ADS7924: STM32 IIC read register no ACK

Hi tom, I used the ADS7924EVM board with my control chip for testing, and connected them with flying wires. The SDA and SCL from the control chip were connected to the SDA and SCL of J10 on the EVM....

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Forum Post: RE: ADC12DJ3200: SYSREF signal question

Hi Eric, R&D said they have tried below code (0x40 → 0x00 ) to turn off sysref receiver and sysref processing, but t he transmission was still out of sync . Could you provide the sample code which...

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