I just finished the additional tests. If all I do is pull the START pin high I do not see a 50 Hz signal on DRDY or any periodic waveform on it at all. The attached logic analyzer capture is our effort to get the clock polarity correct. However the logic analyzer can no longer decode data and notice the DRDY pin moves but does not appear to contain data. It looks like it is stuck in a DRDY function without changing to DOUT in order to echo the MOSI command of 0x06, 0xFF. To get the Xilinx Zynq 7020 SPI bus clock set I am setting the following bits in the Xilinx CR register. BIT 2 = 1 // Third bit clock innactive outside word. BIT 1 = 1 // Second bit clock quiescent high Also I am transmitting extra bytes to keep the SPI Bus open so clock is provided to the 1261 for its response. So my command is actually 0x06, 0xFF, 0xFF, 0xFF. When I only transmitted 0x06, 0xFF the SPI bus would turn off the clock immediately after transmitting the second byte which I thought might be preventing the 1261 from responding.
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