Hi George Sarkees, The behavior as described in the datasheet is what I am seeing on the EVM - see below (the REFOUT waveforms are not great because my logic analyzer has fairly low resolution analog, but you get the idea) Basically, I have set VREFCON = 11b such that the VREF powers down once the conversion is complete or the START pin is brought low. Also I am sampling at 20 SPS. Once the START pin (green signal) is taken low the first time, the REFOUT voltage (blue signal) remains at ~2.048V until the conversion completes (indicated by yellow DRDY toggling). Then I pulse START again, triggering another conversion. The REFOUT returns to 2.048V because the VREF powers back up, then ~50ms later I get another DRDY pulse indicating that the conversion is complete. Note that START was low during almost the entire process the second time, but REFOUT remains at 2.048V until the conversion completes as indicated in the datasheet. Then you can see the powerdown behavior again, due to the 10uF cap on the REFOUT pin. So this should not be a concern of yours, the ADC does wait for the conversion to complete before powering down the VREF. This makes sense because otherwise the conversions would be all screwed up
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