Forum Post: ADS1263: AINCOM level shifter output
Part Number: ADS1263 Tool/software: I am designing with the ADS1263 and want to you the level shift feature to output the (AVCC-AVSS)/2 on the AINCOM pin. I write to the POWER register to enable the...
View ArticleForum Post: RE: TI-JESD204-IP: TI-JESD204-IP: Simulation in Vivado 2023.1
Hi Ameet, Yes, we are following the guidelines specified on the TI204C-IP JESD FPGA IP User Guide. Section 8.6 Testing the Reference Design. The picutre below show the resets signals. Also, the IP...
View ArticleForum Post: RE: ADS7142-Q1: ADS7142QDQCRQ1, ADS7138IRTER, ADS7138QRTERQ1
Hi Arunkumar, These are all newer product there and EOL risk is extremely minimal, we expect them to run to well over 10 years. Please refer to this resource for how TI nomenclature defines COO -...
View ArticleForum Post: RE: AFE7950EVM: configure LMK04828 in AFE7950EVM
Hi Juli, If you can fill out the table below i can create a custom script for you. TX # of TX enabled ? Fs DAC [GSPS] ? Single or Dual Band ? Interpolation ? FB # of FB enabled ? Fs ADC[GSPS] ? Single...
View ArticleForum Post: RE: ADS1263: AINCOM level shifter output
Hi Rachael Parker, The VBIAS behavior is pretty straightforward, so are you sure the command is executing correctly? Have you confirmed that you have successfully set other register settings, and it...
View ArticleForum Post: ADS8568: SPI interface to ATMEGA2560
Part Number: ADS8568 Tool/software: Hi Has anyone been able to interface via SPI an ATMEGA2560 to an ADS8568? In my current application, the ADS8568 is layout to operate in serial mode. Until now I...
View ArticleForum Post: RE: ADS112C04: ADS112C04IPW
Hi Ramin Tavassoli, What are you doing in these images? Also, we are not going to be able to offer much help if you only have a single-channel scope. We really need to see SDA and SCL on the same...
View ArticleForum Post: RE: ADS8568: SPI interface to ATMEGA2560
Hello PowerGuy, Thank you for posting on TI's E2E Forum! The ATMEGA2560 has not specifically been tested, but the ADS8568 uses SPI Protocols CPOL=1, CPHA=0 and has a SCLK speed range from 100kHz to...
View ArticleForum Post: RE: ADC12QJ1600: IBIS model issue
Hi Rob, Thank you for your support. But it seems that i can't log in the link you shared with my personal TI account. Is there any other method i can get the IBIS-AMI model? Or could you please help...
View ArticleForum Post: RE: ADS1263: AINCOM level shifter output
Hi Bryan, I am using the Waveshare AD hat which I know is not supported by TI. I wrote code to read all registers so I can confirm I am writing them properly. I am using 5V supply and internal 2.5V...
View ArticleForum Post: RE: TI-JESD204-IP: TI-JESD204-IP: Simulation in Vivado 2023.1
Hi Daniel< Please remove the *_entity.sv file. It is meant to be used only as a reference for instantiation (as the core file is encrypted). Other than that, everything else should work in...
View ArticleForum Post: ADS8691: Implementation of the converter for data acquisition
Part Number: ADS8691 Tool/software: Hello, I'm writing to you to ask if anyone could help me with a problem I'm experiencing and I'm stuck. I'm driving the ADS8691 with my STM32G431CBU MCU via SPI....
View ArticleForum Post: RE: ADS8691: Implementation of the converter for data acquisition
Hi Laurent, Can you get a clearer screen shot of SDI versus SDO? Maybe zoom in a bit on the 0x28 screen shot to get a clearer idea of how the SPI interface is setup?
View ArticleForum Post: DAC3482: Inverse sinc filter makes no difference
Part Number: DAC3482 Tool/software: We are using DAC3482 and do not notice any difference in the frequency response of our system when enabling/disabling the inverse sinc filter. In both cases, the...
View ArticleForum Post: RE: ADS8691: Implementation of the converter for data acquisition
Hello Tom, and thank you for your invaluable help, because I'm having a hard time here... I'm attaching a zoomed-in image where you can see that in SDO, the register addressed in SDI is repeated but...
View ArticleForum Post: RE: ADC12QJ1600: IBIS model issue
Hi Jingke, Yes, I will close this post and share the model thru email. Please be on the lookout for my email. Regards, Rob
View ArticleForum Post: RE: ADS8691: Implementation of the converter for data acquisition
Hi Laurent, I was hoping you could zoom in on the time base with the o'scope - maybe just the first 16 clocks or so?
View ArticleForum Post: RE: ADS8691: Implementation of the converter for data acquisition
Sorry, I took another measurement.
View ArticleForum Post: RE: ADS8691: Implementation of the converter for data acquisition
Better! If you look closely, you should notice the the phase relationship for SDI and SDO are not aligned. SDO is valid on the rising SCLK (CPHA=0) while SDI is valid on the falling clock edge...
View ArticleForum Post: RE: DAC3482: Inverse sinc filter makes no difference
Hi Hugo, When enabling the inverse sinc filter, you will have to adjust your input level to offet the whole input I/Q rate by the amount of maximum compensation you plan to have. For example, if you...
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