OK, I will fix the clock back to what it was. Clock idle low, innactive outside word and capture falling edge. We have the logic analyzer connected to the 1261 DOUT/DRDY pin, the combined pin. I was not aware the 1261 had a dedicated DRDY pin. I will check with our hardware engineer and get him to pin that out and repeat the START test using that pin. Though I'm curious why the 1261 is not putting data on the combined pin. Maybe if I fix the clock that will work, but before it was only doing zeros or all 0xFF and was not echoing the command (as you are aware already).
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