We continue to try to make this work. You can see the logic analyzer is working in the 4 X 24 clock plot. The uC is correctly reading the values so SPI works. DRDY always goes high after 3X24 clocks. Clock is 392kHz. DRDY is already low when we randomly do the SYNC. It only goes high after the 3rd frame. Why does DRYD always go high after the 3rd frame? If we get it to work, are the 6 channels in frames 2-7 ? thanks
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