Forum Post: RE: ADC12DL2500: Pin termination
Hello Nandini, Please see the datasheet pin descriptions below for SYNCSE and TMSTP For sysref if it is unused it can be left unconnected. Best, Eric
View ArticleForum Post: RE: ADS1247: 18 Channel Multiplexing
Hi ABHAY VASHISTHA, I see that you asked a similar question about the ADS124S08 here:...
View ArticleForum Post: RE: ADS131B04-Q1: SPI Timing
Hi ? ?, Can you send a logic analyzer plot showing the communication signals from/to the ADC? And please identify on those images what you are seeing with the DRDY pin that is not what you expect. It...
View ArticleForum Post: RE: ADS1115EVM-PDK: 4 second connect then disconnect of EVM....
Hi Chuck, Have you been trying to run the ADCPro GUI with the latest version of the EVM (PAMB-based instead of MMB0-based)? This older version of the EVM (hardware using MMB0 controller, and ADCPro...
View ArticleForum Post: RE: ADC12DJ5200-SP: CLK_P/N and SYSREF Input Waveforms
See attached for the input wave form being fed to the ADC CLK_P/n pins from the LMX2615.
View ArticleForum Post: ADS7066: SPI Hardware
Part Number: ADS7066 Other Parts Discussed in Thread: DAC70508 , Tool/software: We are using your ADS7066IRTER and DAC70508ZYZFR in a design. The ADS7066 and DAC70508 devices are on their own...
View ArticleForum Post: RE: ADS1282: Improving transient voltage suppression for geophone...
Hello Jonathan, There are several options that do not require a low voltage (<5V) TVS. Figure 65 in the datasheet suggests adding diode clamps at the ADC inputs. The BAT54 is usually a good choice...
View ArticleForum Post: RE: ADS7038Q1EVM-PDK: Auto-Sequencing doesn't restart after...
Hi Deepak, Thanks for the clarification. After you trigger the CRC error, the SYSTEM_STATUS register should read 0xC2. Can you confirm this? Clearing the CRCERR_IN bit is done by writing a 1 to the...
View ArticleForum Post: RE: ADC12DJ5200-SP: CLK_P/N and SYSREF Input Waveforms
Hi Joseph, If you plan to use an LVPECL style output, then you need to pull the outputs directly to ground, thru a DC path. For example, 150 to 240ohm pulldown on each output leg. The termination...
View ArticleForum Post: RE: ADS8681: SPI CLK to SDO Delay contradicts max. SPI Frequency.
Hi Tom, the CS pin (yellow) has a bit of crosstalk on it coming from the CLK signal. In my opinionen it should not matter, because its amplitude is only around 300-400mV.
View ArticleForum Post: RE: ADS131M04: ADS131M04 Not able to communicate with the IC
Hİ Joachim, We solved the problem, I don't know why, but when I receive power from the computer with PHI, the data I read when the JP9 pin receives LDO 3.3v shows 0x7FFFF, but when I feed the power...
View ArticleForum Post: RE: ADS131B04-Q1: SPI Timing
Can you see this?GC_DLY[3:0] is set 1110b(32768/(4.096*10^6)), but the sample period is set 10ms
View ArticleForum Post: RE: ADS131E08: Read Data with RDATA command and the result is...
Hello Bryan, We use the first and second points you mentioned, and there will be exceptions when reading data. But based on the third point you mentioned, we have adopted a DRDY peripheral interrupt...
View ArticleForum Post: AFE58JD48EVM: An error occurs when automatically launching the...
Part Number: AFE58JD48EVM Other Parts Discussed in Thread: AFE58JD48 , , TSW14J50EVM Tool/software: Hi TI experts, I am trying to use AFE58JD48EVM with TSW14J50EVM. I followed the steps described in...
View ArticleForum Post: RE: AFE58JD48EVM: An error occurs when automatically launching...
I also noticed that the power supply chips U2 and U10 on the AFE58JD48 EVM board were overheating to 100+ degrees Celsius. The power supply pins of the power supply chips are shorted to ground, is...
View ArticleForum Post: RE: TI-JESD204-IP:rx_lane_valid signal are transition from ‘1’ to...
Hi, These errors can either be due to any of the following: 1> the Tx and Rx frame alignment going out of sync (frame/multi-frame errors) 2> signal integrity issues on the board, which can cause...
View ArticleForum Post: RE: ADS131B04-Q1: SPI Timing
1、(CLKIN is set 8KHz)The abnormal DRDY behavior still fetches the correct data, and the in-program read data behavior is triggered by an external interrupt on the DRDY pin. When I run the command to...
View ArticleForum Post: RE: ADS52J90: What does the IDLE_MODE register bit represent?
Hi, With IDLE_MODE set to 1 the data from the transmission stage will be replaced by BC50H
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