Hi Deepak, Thanks for the clarification. After you trigger the CRC error, the SYSTEM_STATUS register should read 0xC2. Can you confirm this? Clearing the CRCERR_IN bit is done by writing a 1 to the bit. I accomplished this with the "set bit" opcode. Afterwards, I read the SYSTEM_STATUS register and read 0xC0 as before the CRC error was triggered, so it is interesting to me that you are getting 0x80 and the SEQ_STATUS bit isn't set anymore. Is there any other configuration you are doing in between after triggering a CRC error? Did you maybe modify the CONV_ON_ERR parameter in the OPMODE_CFG register? Regards, Joel
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