Hi, These errors can either be due to any of the following: 1> the Tx and Rx frame alignment going out of sync (frame/multi-frame errors) 2> signal integrity issues on the board, which can cause all forms of mismatches at the receiver. 3> the reference clocks to the FPGA are drifting (does the FPGA get its clocks from the same root source as the ADC)? 4> it can also be timing related, which worsens as the FPGA temperature rises. Kindly check your timing constraints One option will be to try running the link at a lower rate to see if the problem still occurs. That may give some indication about signal integrity or timing related problems. Regards, Ameet
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