Forum Post: RE: ADS124S08: Thermal pad connection in QFN package with...
Thank You Bryan Lizon86 Sounds very reasonable. Could you please point me to the source of this information? I would like to understand that a bit deeper :)
View ArticleForum Post: AFE4300: Body impedance measurable AFE inquiry
Part Number: AFE4300 Tool/software: Hi, TI expert A customer has an enquiry about body impedance measurable AFE. - Application : AED(Automated External Defibrillator) A customer is using an AFE4300 in...
View ArticleForum Post: DAC chip and evaluation board provided file of DAC38RF82(TSW14J50)
Part Number: DAC38RF82 Tool/software: I bought a DAC38RF82 (TSW14J50) and am testing it with an internal GUI clock, and I get the following error. What is the problem? I checked the jumper settings on...
View ArticleForum Post: DAC38RF82:DAC chip and evaluation board provided file of...
Part Number: DAC38RF82 Tool/software: I can't connect to the DAC when running the HSDC GUI. I used the TSW14J50 capture board, but it doesn't work as the USER guide, so I can't start. Please suggest a...
View ArticleForum Post: ADS1292R: Insufficient sampling rate
Part Number: ADS1292R Tool/software: Hello, TI engineers! I only used one ADS1292R to test one channel of ECG and one channel of respiration. I have a question about the sampling rate of ADS1292R....
View ArticleForum Post: RE: DAC38J82: DAC38J82IAAV
We have used this component (DAC38J82) in several boards before. Also we used a similar component (DAC38J84) which is a 4-ch hw/sw compatible version in some boards. The issue with the mentioned batch...
View ArticleForum Post: RE: TI-JESD204-IP: Issue Synthesizing TI_204C_IP
Hi Sundar, Yes, you can use RTL directly, but the Vivado IP integrator flow does not permit system verilog for that. If you create a verilog wrapper around the top level module and flatten all the...
View ArticleForum Post: ADS7924: Error in datasheet concerning Max input voltage
Part Number: ADS7924 Tool/software: Ref Data sheet for ADS7924 SBAS482C –JANUARY 2010–REVISED SEPTEMBER 2017 Section 6.1 - Absolute Maximum Ratings Analog Input Voltage is quoted as: Min (AGND-0.3)V...
View ArticleForum Post: RE: ADS7830: Reading full range
Just to rule out a possible oscillation - can you look at the input with an o'scope?
View ArticleForum Post: RE: TI-JESD204-IP: TI-JESD204-IP
Hi Hari, The TI JESD IP archive contains reference designs that are built for loopback based testing. For example, you can use the ZCU102*8b10b design for this. Please refer to the TI JESD IP user...
View ArticleForum Post: RE: TI-JESD204-IP: Support for ASIC impelmentation
HI Neel, As of now, the JESD IP supports FPGA implementations only. There are plans to extend this beyond Xilinx to Altera and MicroSemi, but not for ASICs. Regards, Ameet
View ArticleForum Post: RE: ADS7924: Error in datasheet concerning Max input voltage
Hi Andrew, Good catch! Thank you for pointing out this typo on the ADS7924 datasheet. You are correct - MAX would be AVDD + 0.3 for CHx as well as ADCIN. We'll have that changed with the next...
View ArticleForum Post: RE: K value not changing LMFC period in ADS52J90 and TI-JESDC link
Hi Trushal, Kindly let me know the lane rate and frequency of the rx sys clock. The sysref realign counter is incrementing because sysref period needs to be an integer multiple of the multiframe...
View ArticleForum Post: RE: DAC38J82EVM: Issue Synthesizing TI_204C_IP in Block Design
Hi Sundar, Kindly create a verilog wrapper around the top level. The Vivado block design flow does not support system verilog. Regards, Ameet
View ArticleForum Post: RE: ADS7830: Reading full range
ok, just checked with a scope and no oscillation, absolutely steady.
View ArticleForum Post: RE: AMC3336: AMC3336 DC-offset problem
I mean when rising VDD voltage(orange) the clock pin voltage(blue) also rising with it to logic high and after some time the clock appear with first pulse going logic low (the signals are undersampled...
View ArticleForum Post: AFE4490: No voltage across LED_P and LED_N
Part Number: AFE4490 Tool/software: Hi, On the below circuit, Voltage across: LED DRV and TX_SUP Voltage is 5V RX ANA and RX DIG Voltage is 3V. Our MCU is running at 3.3V and when we observed, the...
View ArticleForum Post: RE: DAC8562: DAC Not Responding Even With Supposedly Correct SPI...
I only tested as low as 200khz HW SPI. Software SPI could only go as fast as 166khz
View ArticleForum Post: RE: ADS124S08: Thermal pad connection in QFN package with...
Hi Marcin Mazur, This is defined by our design team during the development of the device, so that is the source of this information. It isn't a hard & fast rule for all devices -Bryan
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