Forum Post: RE: DAC161S997: Inquiry on Loop and Ground Configuration in the...
Hyejun, I'm not sure I understand the need for the isolation between the loop and the DAC161S997 but I think it should be ok. In the transmitter, I generally see the device operating at the same...
View ArticleForum Post: RE: ADS1288: ADS1288
Hi Lagva, One clarification, the THP210 should be operated with +/-2.5V supplies, same supplies used for the ADC. The GND pin of the 4.096V reference and ADC REFN pin connects to -2.5V. Route the...
View ArticleForum Post: RE: DAC7760EVM: Problem to see driver under Windows 11 of SM-USB-DIG
Thomas, I'm running on Windows 11 and am able use the DAC8760EVM (same platform as the DAC7760EVM) with the SM-USB-DIG. First, I've seen similar messages from errors.edgesuite.net, and I think that...
View ArticleForum Post: ADS127L01: Conversion results
Part Number: ADS127L01 Tool/software: Hi, I have setup the device for LL filter and OSR 32 for sampling rate of 512KSPS, we are trying to measure rapid DC voltage changes at a fast rate for our...
View ArticleForum Post: RE: ADC3669: Achieve 1GSPS using interleaving
Hi Kondo, Understood. However, it will be difficult to achieve AC performance specs if you are not familiar with what to do by tying the two analog inputs together and accounting for the gain, offset,...
View ArticleForum Post: RE: ADC12DJ5200-SP: how to use clock chip LMX2594RHAR and...
Hi Xiaoqiu, This network allows for the signal BW from 300kHz to 8.2GHz. The internal ADC capacitance is found in the datasheet specs. You can also refer to the ADC12DJ5200RF datasheet as well....
View ArticleForum Post: RE: TI-JESD204-IP: JESD IP support for Intel Altera FPGAs
Hi Nishie-san, The current status is unfortunately the same. We have been looking at adding JESD IP support for Altera (and MicoSemi) FPGAs, but we won't be able to offer a timeline on when this will...
View ArticleForum Post: RE: ADS131E08: Issue Utilizing the Full Range
Hi again Dale. Apologies for the delay here - things are moving a bit slowly on this project at the moment, but I am working on gathering the info you requested and will write back as soon as I have it.
View ArticleForum Post: RE: DAC8775: Open Circuit Condition
Nithin, I'd asked this before, but what it the model of the transformer you are using? I'm still not sure what the problem is, but can you set the device to enable the buck-boost positive arm and...
View ArticleForum Post: RE: ADC3660: Please review ADC3660 programming.
Hi Miyahara, Please help me understand this part of your sentence above "...when it was NG, and found..." What does NG mean? Your block diagram is fine. If you can share the amp and ADC schematic...
View ArticleForum Post: RE: ADC3660: Please review ADC3660 programming.
PS - we are validating your register writes on the lab bench with design. I hope to have an update by early next week. Regards, Rob
View ArticleForum Post: RE: ADC3642: Reduced output range in single-ended mode
Hi Kevin, Thanks for the additional info. Let me check on this and see if there is anything missing in your reg write sequence. Give me a few days to get back to you. Regards, Rob
View ArticleForum Post: RE: ADC128S102-SEP: ADC128S102-SEP Digital Input Power Sequencing
Hi Aidan, I wasn't able to get anyone to assure that violating the absolute maximum would be okay. Given that, I suggest making sure that the SPI signals are only present on the digital inputs when...
View ArticleForum Post: RE: AFE881H1: UART COMMUNICATION PROBLEM
Yusuf, When the device starts up, the DAC output should be at 0.3V. Even if the device comes up in an error condition, there is an internal circuit that should put out a voltage very close to 0.3V....
View ArticleForum Post: RE: ADC128S102-SEP: ADC128S102-SEP Digital Input Power Sequencing
Joel, thank you for continuing to look into this. It is still relevant for us and would be great to know.
View ArticleForum Post: RE: ADS131E08: Issue Utilizing the Full Range
Hi Daniel Mitchum, Dale is actually out of the office, so our response would be delayed anyway for the next 1.5 weeks -Bryan
View ArticleForum Post: RE: ADS127L21B: Synchronise multiple ADS127L21B
Hello Teddy, Welcome to the TI E2E community. The clock input pin on the ADS127L21B has about 1pF total capacitance. However, depending on your board stackup and layout, the PCB track capacitance will...
View ArticleForum Post: RE: ADS127L01: Conversion results
Hello Anas, Welcome to the TI E2E community. The filter will have a 5 conversion period settling time, but each conversion will show a response to a step input change. Also, using the LL filter with...
View ArticleForum Post: RE: ADS1278EVM-PDK: Interfacing ADS1278EVM-PDK (standalone with...
Hello Yuchen, Yes, you can use modulator mode, but you must create a suitable digital filter in your processor. Please note that you will need to sample data at the modulator data rate, which is...
View ArticleForum Post: RE: ADS52J90: Odd Even ADC (ADe/ADCo) input separation in JESD...
Hi, I understand from experiment that LMFC pulse can not be specifically associated with ODD and Even samples. From various TI forum posts related to similar ADC family, I understood that we need to...
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