Hi, I understand from experiment that LMFC pulse can not be specifically associated with ODD and Even samples. From various TI forum posts related to similar ADC family, I understood that we need to use the TX_TRIG signal. In the TI_JESDC document, there is not help wrt calculating deterministic latency. So if TX_TRIG is generated from FPGA, how much delay we need to consider in order to capture TX_TRIG event (effect) at the output of data receive side of JESD IP ? Hoping to get some help.
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