Dear Neeraj: Customer tested their board found the below 2 issues, and want to know the below issues whether is the root can not configure the DAC in 7 BIT interface mode. Pls. kindly help to give some advice about the below issues. 1. customer configures config1 (reg 0x01) as 0xC01E (bit15 set to 1, i.e. turn on iotest mode), and find that the low 14bit (iotest_results) read-back value of config4 (reg 0x04) is not all 0. The value changes every time the power is restarted, but it is not all 0 each time. The read-back value of bit4 (alarm_from_iotesta) of Config5 (reg 0x05) is 1, which means that the test has errors. 2. Customer found the reading register's bit6 value( 0x05 alarm_dataclk_gone) is always 1, and it's possible dataclk is loss or having mistake. However, tesing the clock is normally from DAC3171 testing. The waveform as below picture: 1). Green signal is data_clk, and blue signal is one bit of 7bit data. 2). The every bit of 7bit data is 1 when the clock is rising edge, and when the clock is updown edge the every bit is 0. 3）. Clock frequency is 200MHz.
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