Hi Neeraj, Thanks for the reply. I've been working on this over the week and I think I've solved it. I was given modified (corrected?) configuration files by an engineer at the TI local distributor in Japan which I've attached at the bottom of this post. I'll run through the procedure which worked for successful link-up and seemingly valid data, as well as a couple of questions I still have. After some trials, I got the FPGA & ADC eval board to link without an interrupt assertion from the Intel JESD IP through the following power-up sequence: 1. Turn on FPGA development board and program object 2. Turn on ADS54J42 Evaluation Board & 500 MHz, -7 dbm reference clock source note: eval board powered by 5V DC source, current ~0.61 A at power-up 3. Load LMK_Config_External_Clock_Modified.cfg in ‘Low Level View’ tab in ADS54Jxx GUI v1.8 4. Load ADS54J40 _LMF_8224_K32_Modified.cfg in ‘Low Level View’ tab in ADS54Jxx GUI v1.8 5. Reset FPGA dev board using switch (S4 CPU RSTn) After step 4, the interrupt signal is asserted and all the other significant link signals (sync, dev_aligned, rx_data_valid) are all low. Upon FPGA restart at step 5, the interrupt signal goes low and the other link signals are high. Here are the signals on Signal Tap after step 5: The data inputs are a 5 dbm, 125 MHz CW input to channel 0 & 0 dbm, 62.5 MHz CW input to channel 1. The data signals seem to be correct, but I just have concerns about the frame assembly described in the datasheet. From this, I assumed the following data sequence from the 256-bit rx_link_data stream: with data0 - data7 being consecutive data samples at 62.5 MHz. I just have a couple of concerns: 1. Are my data samples in correct order? The 2-parallel data stream per channel at 250 MHz are produced using an asynchronous FIFO. 2. About the config files, is there any significance as to why I achieved successful link-up only by configuring the SYSREFDIV register at the end (in ADS54J40 _LMF_8224_K32_Modified.cfg)? Originally, the SYSREFDIV register is set in the LMK_Config_External_Clock_Modified.cfg file, but by doing this i would always have the interrupt signal asserted along with the other link signals high. I'm not sure, but I think this means that the link-up is successful but there is some sort of error. To fix this, I tried moving the SYSREFDIV register setting to the end, and it worked. I also don't understand why this register setting is included at the end of ADS54J40 _LMF_8224_K32_Modified.cfg: 0x10F 0x06 //Disable SYSREF to ADC Did the procedure work because the SYSREFDIV setting must be set after this register setting? To clarify, the SYSREFDIV setting must be 128, so that 500 / 128 = 3.90625 = LMFC clk = 500 / 4 / 32. Also, I left all other config register settings the same from the one sent by the TI local distributor engineer except for: - changing 0x13B setting from 0x80 -> 0x00 in LMK_Config_External_Clock_Modified.cfg - adding 0x13B 0x80 setting at the end of ADS54J40 _LMF_8224_K32_Modified.cfg Apologies for the long post (again) and thank you for any insight you can provide. Regards, Abdul (Please visit the site to view this file) (Please visit the site to view this file)
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