Hi Joel Meraz, As shown in the hardware schematic diagram The AD value of the photoresistor is input through the AIN2 channel. So I tried to read the values of Recent_C_2LSB and Recent_C_2MSB to check if they match the measured voltage values. However, the read register result is 00 So I would like to ask if there are any other configurations that need to be done? Regards, Ziming Yi
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Forum Post: RE: ADS7138-Q1: Abnormal read register value, unable to successfully write register
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Forum Post: ADS7046: CS pin
Part Number: ADS7046 Tool/software: Hi, When the CS pin signal line goes to Hi-Z, what state does the CS pin go to? For example, if the CS pin's internal circuit has a pull-up resistor, the CS signal will not go to an unclear state when it goes to Hi-Z. Best Regards, Nishie
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Forum Post: AFE2256EVM: program help
Part Number: AFE2256EVM Tool/software: i cannnot understand your fpga firmware,like iwhat this part is doing ? ,also,i cannot find the program about Word_alginment,is that one ? could you please give me more sophisticated example of word alignment and data capture verilog program.i am the new FPGA engineering?,thanks for your help.
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Forum Post: RE: AFE2256EVM: program help
also can you give me the image generation example program?
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Forum Post: RE: ADS131B04-Q1: Offset difference between power modes
Hi Dale, Thank you for thinking with us. It took me some days to get parts arranged and find some time to test. ADS131B04 AVCC original supply. MUX1[1:0] set to 0x00. 2 kOhm input resistors removed. Channel 1 input pins shorted to AGND Measured offset error -26.9 µV (Code -188.3) Very close/comparable to earlier measurements with input resistors in place. ADS131B04 AVCC supplied through LDO. MUX1[1:0] set to 0x00. 2 kOhm input resistors removed. Channel 1 input pins shorted to AGND Measured offset error -26.3 µV (Code -184.1) Very close/comparable to earlier measurements without LDO supply ADS131B04 AVCC supplied through LDO. MUX1[1:0] set to 0x01: Thus internal short to AGND. 2 kOhm input resistors removed. Channel 1 input pins shorted to AGND Measured offset error 3.4 µV (Code 23.7) Very close/comparable to earlier measurements without LDO supply and not near the expected typical offset of 0.4 µV. I'm out of options. Tested lowering the drive strength of all SPI lines too in the mean time without noticeable effect. Tested providing an external 8 MHz clock instead of the internal 8 MHz oscillator in the mean time without noticeable effect. Tested adding additional ground plane connections in the mean time without noticeable effect. I think I'll solder a ADS131M04 in place next week as I do not recall seeing this kind of offset errors when using this chip in the past. Kind Regards, Dries
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Forum Post: RE: ADS7028: Read and Write Issue with ADS7028
Hey Joel, surprisingly that actually fixed it. The surprising part is my MCU is TMS320F28377D and initialization code was the following: // Initialize SPI-A // Set reset low before configuration changes SpiaRegs.SPICCR.bit.SPISWRESET = 0; // Enable master (0 == slave, 1 == master) SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; // Clock polarity (0 == rising, 1 == falling) SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; // No loopback SpiaRegs.SPICCR.bit.SPILBK = 0; // Clock phase (0 == normal, 1 == delayed) SpiaRegs.SPICTL.bit.CLK_PHASE = 0; // Set the baud rate (SPI Baud = LSPCLK / (BRR + 1)) SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 49; // (1 MHz) // No high speed mode. SpiaRegs.SPICCR.bit.HS_MODE = 0; // 8-bit character SpiaRegs.SPICCR.bit.SPICHAR = 0x07; // Clear SPI flags SpiaRegs.SPISTS.bit.OVERRUN_FLAG = 1; // Initialize SPI-A FIFO registers // Enable FIFO SpiaRegs.SPIFFTX.bit.SPIFFENA = 0; // Clear FIFO flags SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1; SpiaRegs.SPIFFRX.bit.RXFFOVFCLR = 1; SpiaRegs.SPIFFRX.bit.RXFFINTCLR = 1; // Release FIFOs from reset SpiaRegs.SPIFFTX.bit.TXFIFO = 1; SpiaRegs.SPIFFRX.bit.RXFIFORESET = 1; // Set levels for interrupts, interrupts will not be used SpiaRegs.SPIFFRX.bit.RXFFIL = 1; SpiaRegs.SPIFFRX.bit.RXFFIENA = 0; And this did not work. It normally should have initialized SPI with CLKPHA and CLKPOL 0. But when I changed the phase to 1 like the following, it somehow fixed the issue: // Initialize SPI-A // Set reset low before configuration changes SpiaRegs.SPICCR.bit.SPISWRESET = 0; // Enable master (0 == slave, 1 == master) SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; // Clock polarity (0 == rising, 1 == falling) SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; // No loopback SpiaRegs.SPICCR.bit.SPILBK = 0; // Clock phase (0 == normal, 1 == delayed) SpiaRegs.SPICTL.bit.CLK_PHASE = 1; // Set the baud rate (SPI Baud = LSPCLK / (BRR + 1)) SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 49; // (1 MHz) // No high speed mode. SpiaRegs.SPICCR.bit.HS_MODE = 0; // 8-bit character SpiaRegs.SPICCR.bit.SPICHAR = 0x07; // Clear SPI flags SpiaRegs.SPISTS.bit.OVERRUN_FLAG = 1; // Initialize SPI-A FIFO registers // Enable FIFO SpiaRegs.SPIFFTX.bit.SPIFFENA = 0; // Clear FIFO flags SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1; SpiaRegs.SPIFFRX.bit.RXFFOVFCLR = 1; SpiaRegs.SPIFFRX.bit.RXFFINTCLR = 1; // Release FIFOs from reset SpiaRegs.SPIFFTX.bit.TXFIFO = 1; SpiaRegs.SPIFFRX.bit.RXFIFORESET = 1; // Set levels for interrupts, interrupts will not be used SpiaRegs.SPIFFRX.bit.RXFFIL = 1; SpiaRegs.SPIFFRX.bit.RXFFIENA = 0; No idea why though. If you have any ideas why this happened, I would appreciate it. Thanks, regards. Ege
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Forum Post: RE: AFE882H1EVM: EVM application usage
Hi Joseph , Just for reference i taken screenshot without connecting the EVM. That is the reason it is in demo mode. I installed the drivers now i am getting Vout(i.e 0-2.5V), but not getting XTR_Out(i.e Voltage out), HART Output even though i enable in application.(I set the jumper position to select the XTR_out from Applicaion). Best Regards Vamshi
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Forum Post: RE: ADS7845: Touch screen driver delivers crappy values
Hi Jonah, Apologies for the delay, ill look into issue over the weekend
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Forum Post: RE: AMC7834: IOVDD Amplitude
Hi Erin, Sorry for the delay. Please find the results below. It looks like DAC setting Adress 0x30 - 0x32 is effecting the results in addition to clamp setting. Befor setting clamp voltage | #1 IOVDD:3.269V(typ) / 3.289 V(max) / 3.243 V(min) AVDD:5.0 V(typ) /5.023 V(max) / 4.982 V(min) DVDD:4.99 V(typ)/5.022 V(max) / 4.984 V(min) AVCC:4.99 V(typ)/ 5.042 V(max) / 4.969 V(min) AVSS:-5.025 V(typ)/ -5.055 V(max)/ -4.984 V(min) After setting clamp voltage | #2 IOVDD:3.277 V(typ) / 3.498 V(max) / 3.099 V(min) | Amplitude getting larger AVDD:5.001 V(typ) / 5.018 V(max) / 4.982 V(min) DVDD:5.001 V(typ) / 5.018 V(max) / 4.982 V(min) AVCC:5.001 V(typ) / 5.021 V(max) / 4.961 V(min) AVSS:-5.025 V(typ) / -5.054 V(max) / -5.01 V(min) Behavior Customer Observed Except for #4, IOVDD amplutude get larger (The voltage on #2 above) Start-up (#2) After setting below (Register settings except for default are listed) (#2) Item Address Parameter Data 1 0x02 Power Mode 0002 2 0x10 AMC Configuration 0 1300 3 0x12 ADC MUX 4F00 4 0x16 DAC Range 0005 5 0x17 CLAMP Configuration 0000 6 0x1C DAC/ADC Trigger 0001 DAC1-3 set to 0x333(-4V) (#1) When 2 and 3, set bit0 (DAC12-CLAMP) or bit1(DAC34-CLAMP) to 0->1 on Adress(0x17) CLAMP Configuration When 2 and 3, set any of DAC1-3 to 0x000(-5V) (#2) Please let me know any setting of the possible cause. Is there any effect from VCLAMP 1/2 pin? Right now, there's pull up voltage applied. Best regards, Kazuki Itoh
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Forum Post: RE: ADS131E08: Issue Utilizing the Full Range
Dale, normally AINxP is driven down to 0V through an opamp but I also tried shorting AINxP directly to AGND and got the same negative counts value. For RAW data, are you asking for data in hex? To answer some of your earlier questions: 2. We are running in 24-bit mode since we are reading at 1kHz and we do have the internal reference enabled because we see 2.4V at the output and confirmed PDB_REFBUF is enabled. 4. I measured the internal MVDD and test signal on the board used for case 2 for all 8 channels.
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Forum Post: RE: ADS1291: It's unclear exactly what passives are required on the input side into INP/INN
Hi Kyle, Thank you for your post. The ADS1292R is marketed primarily for ECG applications, either for 2 ECG channels, or for 1 ECG channel and 1 Respiration channel. Of course, any bio-potential signal can be measured by the same IC (provided the SNR is sufficient), but the suggested signal chain components and how they map from electrode input to INxP/N pin is done with ECG and respiration measurements in mind. The channel 1 circuitry on the EVM is designed as the respiration receiver channel. Since you only need to evaluate one EEG channel, I would suggest only using channel 2. This channel is DC coupled and only uses a first-order antialiasing filter in the path. By default, IN2P maps to P5.3 ("ELL") and IN2N maps to P5.1 ("ERA"). In the GUI, use the Scope, Histogram, and FFT tabs to analyze the data. The 4.7-nF caps between PGAxP and PGAxN are additional anti-aliasing at the output of the internal gain stage. This is detailed in the ADS1292R datasheet. Regards, Ryan
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Forum Post: RE: ADS1291: Can the positive and negative electrodes of each channel be captured on two different battery powered devices and then be combined after in post processing software?
Hi Kyle, Yes, that was a confusing question. Can you try to rephrase? Regards, Ryan
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Forum Post: RE: ADS1299-4: About resistance measurement function (LOFF(AC))
Hi Ryu, Thank you for your post. May I ask who is the end customer? It is possible that you are noticing power-line noise interference when you reduce the LOFF current magnitude to 24nA. When the current is increased to 6µA, the noise is probably still there, but less noticeable. This article may help explain some techniques which would improve the accuracy of the impedance measurement using AC lead-off current sources: Signal Chain Basics #149: How to accurately measure electrode impedance for lead-off detection in ECG systems - Planet Analog Regards, Ryan
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Forum Post: RE: ADS1298: Questions about Lead-off detection
Hi Foo Bar, Thank you for your post. I have a few suggestions you can try: Disable all LOFF_SENSN and BIAS_SENSN bits. These are not needed if the INxN pins are externally shorted to AVSS. Close the feedback loop of the RLD amplifier locally by connecting RLDOUT to RLDINV. You can reference the ADS1298 data sheet and User Guide for component recommendations. It is important for the RLD to function properly in order to establish a consistent common-mode voltage. This ensures the input voltages will remain within range of the internal PGA and avoid saturation. Series input resistors can be reduced to 10k. The sinc3 digital filter provides a low frequency cutoff based on the data rate. Resistor based LOFF (bit 4 = 1b) does not use the ILEAD_OFF setting - that setting is only for the programmable current sources. R-based LOFF produces a current equal to approximately (AVDD-AVSS)/(2x9.9MΩ). Regards, Ryan
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Forum Post: RE: ADS131M06-Q1: ads131m02
e2e.ti.com/.../ADS131schematic041825.pdf
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Forum Post: RE: ADS131M06-Q1: ads131m02
We used a Logic analyzer to take these traces. DRDY is still stuck high. Top trace glitch shows DRDY is connected. Middle trace reads 6 channels but all are 0. Bottom trace reads STATUS. We ignore DRDY since always high, even if we wait long time. Is ADS SCHEMATIC CORRECT bottom left? DO WE NEED TO PRESET REGISTERS?
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Forum Post: AMC131M03-Q1: ads131m04
Part Number: AMC131M03-Q1 Other Parts Discussed in Thread: AMC131M03 Tool/software: hi my doubt is, in the AMC131M03 it will send 5 words of data during read from MCU. since im using 24 bit data length. the 3 adc data will come as 24 bit. i want to confirm that the 1st and 5th word, response and crc also will come as 24 bit , when the data length register is configured as 24 bit. or it will be 16 bit data. please clarify this doubt
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Forum Post: RE: AFE4400: AFE4400
What would be the suitable wireless connectivity microprocessor or microcontroller which could be used to integrate these AFE's along battery and memory module?
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Forum Post: TI-JESD204-IP: VHDL Wrapper for TI-JESD204 IP
Part Number: TI-JESD204-IP Tool/software: Hello, I am trying to integrate the JESD204 core into my design. As my primary language for the design is VHDL I tried to create a wrapper around the IP. I am using VIVADO 2022.2, as I am constrained by other IPs of the design. After failing to make the system work, I replicated the example provided and started using VHDL from the top layers up to the TI_204c_IP_Ref block. This works. See the picture below on the design hierarchy: The simulation logs show the following setup: I need to separate the TI JESD204 IP and have it as an independent block to help me with integration and verification. So I created a VHDL wrapper, that use a SystemVerilog Wrapper which instantiates the SVP file alone. I moved the rest of the Reference code functionality to external VHDL modules. I used the intermediate SystemVerilog Wrapper just as a precaution of not changing language domain on the encrypted IP. The simulation hierarchy is as follows (note that I am using VHDL-2008 in this case) The problem is that although the first design simulates correctly, the second one with the wrapper does not. Seems that all the output signals of the IP are 'U', 'Z' or 'X'. I tried to use the MGT_GPIO signals from the GTH wrapper to send them to the top layer and observe if the signals reach the top level, but this also does not work as the signals continue to be in the 'U' state. Example signals that are undefined or tri-stated are the Q/CPLL Lock signals for example (but seems all outputs are in the same such state). It seems to me that the IP is not connected for some reason. Simulation also starts a lot faster in this failing case. I also did the same architecture with a small test block to do the same wrapping methodology for a sample System Verilog, and the I/O seems to work as expected. Please see also that in the failing design VIVADO hierarchy the second layer and below of the hidden nodes (including the GTH driver) are grayed out. Although I can modify the GTH, there seems to be something different. VIVADO does not complain about anything. The wrappers also pass the constants (through Generics) from VHDL to SV. Can you provide any insights of what could be wrong, or if I must use a different approach? Thanks in advance, Ilias
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Forum Post: RE: ADS1298: DRDY pin not going low although the other functions working well
Hi Ryan, ofc the sequence is like expected. The FAQ above, only the step 5 and 6 is not work for me, my DRDY doesnt toggle at all. And these things about SPI transfer is just okay. And here is my schematic!
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