Chandana We just noticed a problem with drivers that needed to be installed for this EVM GUI (the AFE881H1 and AFE882H1). Go to this E2E post: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1495440/afe882h1evm-afe882h1evm-supporting Hopefully, the download from the DAC8811EVM works for you. Let me know if you have problems. Joseph Wu
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Forum Post: RE: AFE882H1EVM: How to enable DAC and HART using AFE88xH1EVM application
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Forum Post: RE: AFE11612-SEP: Queries Regarding ADC Reference, ENOB, AVcc, and Remote Temperature Inputs
Hi Dhir, There should be no issue with leaving the DACs floating, especially if you do not intend to use them. By default, the DACs are in a power off condition. If you want to terminate these outputs, then a 10k resistor to ground would be a safe way to do so. 1. The temperature sensing channels only work with diodes as far as I can tell, not thermocouples. They also cannot be used as general ADC inputs. 2. There is a "preferred" order in the datasheet of IOVDD, DVDD/AVDD, then AVCC. It's fine if DVDD, AVDD, and AVCC go on at the same time, and they can use the same power supply. IOVDD doesn't necessarily have to come on first, but it is preferred. VREF is fine coming on at the end of the sequence. 3. Each channel uses the same ADC, but goes through a MUX. There may be slight offset error or gain error differences between each channel, but overall each channel should be nearly the same. I recommend calibrating each IC, as the ADCs will have different characteristics. Thanks, Erin
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Forum Post: RE: DAC8742H: Does DAC8742H has passed the physical layer test of Fieldbus foundation
Hi Thong, Apologies for the late response, Joe should get back to you within the next week. Thanks, Erin
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Forum Post: ADS1291: It's unclear exactly what passives are required on the input side into INP/INN
Part Number: ADS1291 Tool/software: I see on the layout examples and the development kit that there are many passives on the input lines It looks to me like just a 4.7 nf is required and its suggesting some patient protecting resistors, is that correct? When i see the typical application it has an example with no passives if not using the respiratory functions. Is this example only relating to respiration? Now when i look at the development kit im a bit taken back. Out of these options, assuming i just want to use 2 electrode, one lead eeg. On my design i am just using IN1P and IN1N including the 4.7nf cap. On the development kit i have been using ERA and ELA but this doesnt seem to match with what i intend to do. It looks like I should be using ELL and ERA but on the development software my options are ● ECG Lead I ● ECG Lead II ● ECG Lead III ● ECG Lead aVR ● ECG Lead aVL ● ECG Lead aVF I'm a bit confused reading through the documentation how these map to IN1P and IN1N. Any help is appreciated.
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Forum Post: RE: DAC7644: The marking of DAC7644E problem
Hi Suri, I'm looking into this now, and I'll hopefully have a definitive answer for you next week. Thanks, Erin
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Forum Post: RE: TPL0501-100: About the GND reference on TPL0501-100
Hi Bruce, According to the Absolute Maximum Ratings table, the only requirement for the pins is they must be greater than 0V and less than VDD. In the Power Sequencing, the datasheet specifies: "Protection diodes limit the voltage compliance at terminal H, terminal L, and terminal W, making it important to power up VDD first before applying any voltage to terminal H, terminal L, and terminal W." This means that you could run into issues if you do not connect the ground references. These pins should not be left "floating" in reference to the VDD and digital voltages. Thanks, Erin
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Forum Post: ADS1298: Questions about Lead-off detection
Part Number: ADS1298 Tool/software: Hello, We are using the ADS1298 and are having some issues with implementing leadoff detection. We set up leadoff detection for DC, using the threshold of 95% and 5%, 12nA, and pullup/down mode. We are finding that the EEG signal is no longer usable in this configuration, which is doubly unfortunate because the leadoff works great. Is this to be expected? Our input conditioning is just an RC LPF. Is there something else we can try? Here is the schematic for the EEG: Here is the code that sets all the ADS registers: ADS_WREG (CONFIG1, 0x46 ); //No daisychaining, low power mode, no clock output, 250Samples/s ADS_WREG (CONFIG2, 0x00 ); //not using test signal, turn all off ADS_WREG (CONFIG3, 0xCC ); //internal reference, no RLD ADS_WREG (LOFF, 0x17 ); for ( int i = 0 ; i < NUMBER_OF_ADS_CHANNELS ; i ++ ) { ADS_WREG (CH1SET + i, 0x10 ); //Gain of 8, normal operation for all channels } ADS_WREG (BIAS_SENSP, 0xFF ); //bias correction on ADS_WREG (BIAS_SENSN, 0xFF ); //bias correction on ADS_WREG (LOFF_SENSP, 0xFF ); //All on ADS_WREG (LOFF_SENSN, 0xFF ); //All on // ADS_WREG(LOFF_FLIP,0xFF);//All flipped ADS_WREG (GPIO, 0xF0 ); //led on ADS_WREG (MISC1, 0x00 ); //not using any functions related to misc1 //skip RESP, defaults ok ADS_WREG (CONFIG4, 0x00 ); //No respiration detect, one-shot mode, LOFF Comp enabled //skip WCT1 and WCT2
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Forum Post: RE: ADS7028: Read and Write Issue with ADS7028
Hi Ege, It seems like your SPI mode configuration is incorrect on your controller. By default, the ADS7028 operates in SPI Mode 0 (CPHA = 0, CPOL = 0), where SCLK idles low while ~CS is inactive, and data is captured on the leading edge (rising edge in this case). So the ADS7028 device reads in SDI data from the controller on SCLK rising edges. Because of this, a certain setup time is necessary to ensure SDI is stable before the rising edge of SCLK, and so data for the next rising edge of SCLK is usually changed on the previous SCLK falling edge. At the moment, it looks like SDI changes at the same time as the SCLK rising edge, so the setup time is being violated. This should be relatively easy to change. This should fix your issues assuming everything else is correct. Let me know if you have any additional trouble. Regards, Joel
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Forum Post: RE: DAC5681Z: How to increase output gain.
Hi Aiden, Try a higher output frequency, the ADT4-1T+ transformer as a low end BW of 9MHz. Or switch out the transformer that can cover a lower frequency range. Passing a 10kHz signal thru the ADT4-1T+ won't work. Regards, Rob
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Forum Post: RE: DAC7644: The marking of DAC7644E problem
Hi Suri, This is a datasheet error. All devices should have "DAC7644E" as the device marking. None of the variants will have a "B" marking, and the datasheet is currently being updated to reflect this. Thanks, Erin
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Forum Post: ADS1299-4: About resistance measurement function (LOFF(AC))
Part Number: ADS1299-4 Tool/software: Hi team, I am reposting this because I am not getting a reply. I want to measure the resistance in the following schematic. I posted only one channel, but I am posting the real circuit because I thought it was possible that other channels may have been affected. I actually measured 3 channels in parallel. If I set the current flowing for resistance measurement to 6uA, the voltage will saturate, I am trying to set the current to 24nA, but in that case the voltage will fluctuate. What is the cause of the fluctuation? Which voltage should I use to calculate the resistance? (Peak voltage? Average of fluctuating voltages?) Best Regards, Ryu.
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Forum Post: RE: DAC5681Z: How to increase output gain.
Hi Rob, I fully understood your explanation, so I tested with 10MHz. Below is a snapshot. Thank you.
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Forum Post: RE: AFE11612-SEP: Queries Regarding ADC Reference, ENOB, AVcc, and Remote Temperature Inputs
Hi Erin, Thanks for the clarification. Regarding the power on sequence, I plan to use the internal 2.5V reference. Could you please elaborate why is the power sequence preferred and what sort of issues can occur if power sequence isn't followed? Also, could you please help me with another query I had regarding the TMS570 MCU in another post?
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Forum Post: RE: TPL0501-100: About the GND reference on TPL0501-100
Hi AE, May I ask, if two GND pins are both connected to ground, but they do not share a common ground reference, what kind of impact could this cause? Best Regards
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Forum Post: AMC131M01: Issue with DCDC Cap Voltage
Part Number: AMC131M01 Tool/software: As per our understanding we believe after powering up the chip we should get DCDC_CAP voltage indicating successful power up. But, we are not getting any voltage at that pin.
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Forum Post: RE: AFE11612-SEP: Queries Regarding ADC Reference, ENOB, AVcc, and Remote Temperature Inputs
Hi Dhir, I don't recall exactly what could happen if they are not sequenced correctly. If a customer wants to do an unpreferred sequence, we generally recommend doing a device reset (either through the RESET pin or by writing to the RESET register). I haven't had anyone come back with issues when using a reset. I also helped out with the TMS question. I left it open in case the microcontroller team has anything they want to add, not sure why they haven't gotten to the question yet. Thanks, Erin
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Forum Post: DAC80501: Requests for a Detailed Data of the Sink Current Capability (at Zero Code)
Part Number: DAC80501 Tool/software: Hello. This is Kwonjoon Lee from Samsung Display. I would like to request a detailed data of the sink current capability in Figure 7-33, 7-34, and 7-35. (Detailed Question) 1. What are the output voltages of the zero-coded DAC in the condition that the sink currents (from the Load to the DAC) are 0.15mA and 2mA, respectively. Please provide the above-mentioned output voltages of the DAC for the cases of Figure 7-33, 7-34, and 7-35. Best regards, Kwonjoon Lee
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Forum Post: RE: AFE11612-SEP: Queries Regarding ADC Reference, ENOB, AVcc, and Remote Temperature Inputs
Thanks, Erin!
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Forum Post: AFE2256: AFE2256 Generating Gate Driver Signals
Part Number: AFE2256 Tool/software: Hello, I would need clarification about section 7.1.2: Generating Gate Driver Signals from the AFE2256 of the AFE2256 ROIC data sheet. First, about the SDOUT signal, is the data sheet suggesting the following electrical connections between the ROIC, the FPGA and the Gate Driver? If correct, I see the need to consider isolation between the ROIC/FPGA and Gate Driver junction when having the ROIC communicating to the FPGA on the SDOUT pin.. What's your point of view on this? Regarding the PROBE GATE DRIVE signal ( PROBE_SIGNAL field value (Register 5Ah), 40h) sent by the AFE2256, I understand it to only be a rising and falling edge. I understand this rising and falling edge to be used by the FPGA to trigger on the same line signals from the FPGA to the Gate driver, for example: start a line scan, send a clock signal or others Is that the way it should be working? Thanks for your inputs on this!
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Forum Post: RE: ADS7138-Q1: Abnormal read register value, unable to successfully write register
Hi Joel Meraz, Good news!! After configuring the registers according to the MANUAL MODE process, I directly set the 01 register to 0x2A, I modified the code for the startup frame and sent it in the following format: Start signal+7-bit device address (0x13)+1-bit read flag bit (1)+ACK+2 bytes of ADC data The values read are as follows: It seems that the value read is the AD value. And as mentioned earlier, in Method 2, I also successfully read the value of RECENT_C0_SB/MSB, which matches the AD value So the current reading of the AD value from the AIN0 channel has been successfully completed. Thank you very much for your guidance and assistance. But then I encountered a new problem, and I will provide a detailed explanation of the situation in the next post Regards, Ziming Yi
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