Part Number: ADCS7476 Tool/software: Hi team, My customer is evaluating ADCS7476, and there is a question as below: How many leading zeros on SDATA, three or four? I noticed that the wordings show four leading zeros but the picture shows only three leading zeros (Z2, Z1, Z0). Does the configuration of ADC121's SDATA be same with ADCS7476? How many leading zeros of ADC121? Best Regards, Ryker
↧
Forum Post: ADCS7476: Serial Interface Timing Diagram
↧
Forum Post: ADS1292R: 3 lead ECG input circuit - coupling and anti-aliasing
Part Number: ADS1292R Tool/software: Hi TI team, I was recently studying the reference design for the ADS1292R that you are sharing in this document (page 9): https://www.ti.com/lit/ug/tidu875/tidu875.pdf?ts=1732700470600 This made me wonder whether you could tell me why is there a difference in copupling between channels? Both the first and the respiration inputs are AC coupled, while the second input is DC coupled. I did also notice that the anti-aliasing filtering is applied only to the 2nd input. What are design guidelines for choosing the coupling method and applying the aa filtering? Looking forward to your reply, Piotr Ładnowski
↧
↧
Forum Post: ADS131B26Q1EVM-PDK: ADS131B26Q
Part Number: ADS131B26Q1EVM-PDK Tool/software: Hi, Where can we download the Altium schematic and layout files for this please?
↧
Forum Post: RE: ADS125H01: Background to why CRC is implemented
Hi Shinichi Inoue, In noisy electrical environments such as factories, it is possible for the digital communication to become disturbed. This is similar to how noise can affect analog signals and cause inaccurate measurements, noise can also couple into the digital traces and cause communication errors. CRC is one method to detect this behavior. We implement CRC in many of our ADCs because it is a simple method for the user to detect some digital communication errors. -Bryan
↧
Forum Post: RE: ADS1158: Output Code for Single-ended
Hi user5163865, [quote userid="336910" url="~/support/data-converters-group/data-converters/f/data-converters-forum/1443766/ads1158-output-code-for-single-ended"] In the single-ended case, I think the input range is AINx - AINCOM. I think this is essentially a pseudo-differential input, is that correct? For example, in the following setting +VREF=2.5V, -VREF=0V AINx = 0 to 2.5V 1. When AINCOM = 0, the output code is 0 to 0x7FFF 2. When AINCOM = +VREF/2, the output code is 0x8000 to 0x7FFF [/quote] These statements are correct. The ADS1158 differential input range extends from +1.066*VREF to -1.066*VREF, so if your input signals are single-ended you are only using the positive half of the ADC codes. -Bryan
↧
↧
Forum Post: RE: ADS114S08B: ADS114S08B noise test issue
Hi Jimmy WANG, The schematic you sent does not include any protection components e.g. TVS diodes, that would protect against transient voltages. So yes it makes sense that the board did not pass your tests Consider using something like TVS3301, which is a 33V, bidirectional diode. There are also other options that have lower standoff voltages (down to 5V) and/or unidirectional -Bryan
↧
Forum Post: ADC3669EVM: EVM PCB files
Part Number: ADC3669EVM Tool/software: Would you please provide the latest PCB design files (s/d, layout, bom) for the ADC3669EVM? They don't appear to be in the product folder at this time. Thanks! Steve
↧
Forum Post: DAC39RF10EF: Can DAC39RF10 manage data not encapsulated on JESD204 protocol?
Part Number: DAC39RF10EF Other Parts Discussed in Thread: DAC39RF10 Tool/software: Hello, We are testing DAC39RF10 IC and we would need to know if the following configuration is possible: - 1 -> PRBS generator inside one FPGA (generating PRBS31 data) - 2 -> PRBS generator directly attacking only one GTH transceiver (on UltraScale FPGA). So only one lane of the DAC is used. - 3 -> Encoding 8B/10B is used (configured inside the transceiver) - 4 -> JTEST register is set to 0x4 (PRBS31 encoding) - 5 -> Data is not encapsulated in JESD204 protocol. This means that no JESD204 protocol is used . This is the main doubt we have about our setup. We directly attack GTH transceivers with PRBS generator and 8b/10b encoding. So data received by the DAC is not encapsulated on JESD204 . - 6 -> Activate BER_EN to check errors during communication We have done several tests and through the GUI for the DAC, we see that BER error counters goes to 0xFF instantly after enable JESD_EN bit on corresponding register. Does the DAC require data received to be encapsulated on JESD204 protocol?? If not, Do we have to use all lanes (16) to work with JMODE0 , even when JTEST mode is set to 0x04 (PRBS31)?? Thanks by advance! Regards
↧
Forum Post: RE: ADC3669EVM: EVM PCB files
Steve, which revision?
↧
↧
Forum Post: RE: ADS124S08: Use the ADS124S08 to replace AD1248
Hi Chen Alex1 Some comments: Seems like you have two different "grounds": GND_EX and EX_AGND. I would have expected a single ground e.g. DGND, to which all other voltages are referenced. For example, AVSS, AVDD, and DVDD should all be referenced to DGND. REF is the exception, see the next item You can follow the guidelines below for using a bipolar supply with the ADS124S08 (this is from the datasheet). Note how the reference circuits are connected to AVSS, not DGND (your You might consider adding a pull-up resistor on the RESET pin to ensure the ADC starts up in a known state I don't see the need for the pull-ups on DOUT and DRDY I don't see any biasing on the TC inputs. How do you plan on keeping the TC voltage in the input range of the ADC? Normally this is accomplished by using pull-up/pull-down resistors, which also provide open wire detection We recommend using C0G/NP0 caps on the inputs, for best performance. The X7R caps are okay on the supplies for decoupling/bypass -Bryan
↧
Forum Post: RE: ADC3669EVM: EVM PCB files
Chase - thanks for the quick response! We'd need the revision that is currently available for ordering here: https://www.ti.com/tool/ADC3669EVM We don't have an EVM in hand yet.
↧
Forum Post: ADS8674: How to add the channel adress in Output Data
Part Number: ADS8674 Tool/software: In our application, data is very rarely corrupted. Only on a few devices and less than once a day. The ADS8674 is operated in MAN_Ch_n mode as described in the datasheet on page 46. The first 16 bits of the SDO data should be zero, but this is not the case. This may be due to EMI or mechanical connection problems. In this case we discard the data. To improve this sanity check, we would like to enable the addition of the channel address to the data by setting the SDO bits to 01 in the "Feature Select Register". But it is not clear to me where data bits 8-5 of table 13 are in the data stream. Do we need to continue clocking after the 32nd falling edge of the SCLK signal in Figure 102? In that case we could not keep the 500ksps right? Thanks.
↧
Forum Post: RE: DAC8775: Buck-Boost converters not starting at elevated temperatures
HI Henrik, Joseph will review your questions and get back to you soon. There may be a delay in response due to the thanksgiving holiday. Best, Katlynne Jones
↧
↧
Forum Post: RE: DAC43204: I2C about DAC43204 and CG5162
Hi Gary, Can you try using one of the non-broadcast addresses for the DAC43204? The device should lock the device address after one successful command with one of the 4 addresses. I'm curious if this will change the behavior. Best, Katlynne Jones
↧
Forum Post: RE: ADS1298R: ADS1298R VCM
Hi Jejomar, Yes, the common-mode signal derivation occurs after the PGA output in the ADS1298. This essentially acts as a buffer for each of the electrode inputs since there is no common-mode gain through the PGA. Only the differential signal between INxP and INxN will see the gain of the PGA. I do not understand what is meant by the following: [quote userid="392789" url="~/support/data-converters-group/data-converters/f/data-converters-forum/1438295/ads1298r-ads1298r-vcm/5537394#5537394"]VCM is then put into negative inputs. For this, the VCM could be derived from the same inputs or from different ones for the testing purposes?[/quote] VCM is typically connected to the RLD amplifier inverting input. The DC bias for the body is connected to the non-inverting input. If VCM is derived from the 3 primary electrodes (RA, LA, LL), it can also function as a WCT voltage reference for the V1-6 chest electrodes. This would connect to the INxN input for those channels. Regards, Ryan
↧
Forum Post: RE: AMC1336: AMC3336 Full Scale
Hi Daniel, Thank you for your question. It is definitely possible with some adjustments. The differential input voltage to the device is +/-1V as described below: The first option is to use a voltage divider. Divide the voltage in half so it is within the FSR of the device. Or, if your input range is 0-2V, you could shift your input down 1V so it swings from -1V to 1V. Please let me know if there are further questions. Best regards, Eva
↧
Forum Post: RE: ADS1299: SRB1 and SRB2 in standard configuration
Hello Raja, Thank you for your post. SRB1 and SRB2 can be shorted together for multiple ADS1299 devices. One common reference signal can be routed into all negative inputs by connecting it to both devices' SRB1 pin. Likewise, SRB2 pins can be shared if the reference electrode is to be chosen from either device. Otherwise, if the reference electrode will always come from Device 1, it is not necessary to connect the SRB2 pin of Device 2. Regards, Ryan
↧
↧
Forum Post: RE: ADS7953EVM-PDK: ADS7953EVM-PDK MMB0 drivers
Hi Naji, From what I can tell at the moment, Mouser and Digikey only have the older version available for purchase. You can buy the newest EVM directly from TI.com with the link I included above however. Regards, Joel
↧
Forum Post: RE: ADS1292R: 3 lead ECG input circuit - coupling and anti-aliasing
Hello Piotr, Thank you for your post. The RESP_MODP/N pins are outputs which are transmitting an excitation signal to the body. This excitation signal is modulated by the slow changes in thoracic impedance due to patient respiration. This same signal is measured by through the IN1P/N inputs and demodulated to reveal the respiration impedance waveform. Both the TX and RX paths are AC-coupled to prevent DC current from flowing as only the AC signal is of interest. Typically, an antialiasing LPF is not used here as any added impedance in the path will add noise to the sensitive measurement. ECG inputs can remain DC coupled. The common-mode voltage is typically established by the driven RL electrode such that the input signals are within range for the PGA on each channel. A single pole LPF can be added here with a cutoff ~ 10 kHz. For more details, please refer to the ADS1292 device data sheet. Regards, Ryan
↧
Forum Post: RE: AFE4404: Design review
Hello, Thank you for your post. Our product line is only responsible for the AFE4404. You can create a separate post to have someone review the power circuitry. The I2C pins are missing pull-up resistors to the IO_SUP. Please connect 10kΩ pull-up resistors for I2C_DAT and I2C_CLK. You can also use 10kΩ on nRESET for consistency. The remaining connections to the AFE look mostly correct. The decoupling capacitor designators do not match the PCB placement notes, but the values and layout recommendations are ok. Regards, Ryan
↧