hi Bryan could you help to check the schematic is correct? thanks
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Forum Post: RE: ADS124S08: Use the ADS124S08 to replace AD1248
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Forum Post: RE: BP-ADS7128: USB Port not detected
Hi Joel, It went back to the Acctrl. In any case it had the same result.
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Forum Post: RE: TSC2007: I2C pin level at POR
Thank you. Just to confirm, is it correct that the IC will not break down even in the case of the circuit and waveform shown below?
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Forum Post: ADS1158: Output Code for Single-ended
Part Number: ADS1158 Tool/software: Hi, Sorry for the basic question, but I would like to know about the following question from a customer. "Is the full-scale range when used in single-ended half that when used differentially?" Looking at Table 7 in the datasheet, INPUT SIGNAL VIN = ADCINP - ADCINN In the single-ended case, I think the input range is AINx - AINCOM. I think this is essentially a pseudo-differential input, is that correct? For example, in the following setting +VREF=2.5V, -VREF=0V AINx = 0 to 2.5V 1. When AINCOM = 0, the output code is 0 to 0x7FFF 2. When AINCOM = +VREF/2, the output code is 0x8000 to 0x7FFF Is this correct? Best regards, Hiroshi
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Forum Post: RE: Excess THD in DAC8822 circuit used as audio DAC
Hi Marco, Does -1dBFS show to the same issue? How about -3dBFS? I am surprised that the supplies would be showing the same harmonics. The reference buffers should basically be driving a static load to ground. What happens when you isolate reference for DACA? As you only buffer the reference for DACB, a glitch on the 14.3V reference would also cause a glitch on REFB.
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Forum Post: RE: ADS7953EVM-PDK: ADS7953EVM-PDK MMB0 drivers
Hi Joel, thank you for your prompt response. Is this version available at common suppliers? I have reached Mouser recently, the tech agent was not able to confirm that the version they have in stock is the same as pictured in your website!!! The picture shows an MMB0 instead of showing the newer version. I was hesitant to buy new one.
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Forum Post: RE: ADS127L11: Differential OPAMP suggestion
Hi Keith, Thank you very much for your replay. All clear now. Regards, Iouri
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Forum Post: RE: ADS7865: Power-up sequnce/down sequence
Hello Yolanda, Thanks. I didin't notice that BVdd is specified as <1.5 x AVDD in abs max. Regards, Satoshi Obata
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Forum Post: RE: TSC2003: Regarding TSC2003 sensor reading failure
Hi, I understand. Are there any other solutions besides adjusting the voltage startup time of the SDA and SCL lines and changing the resistance value of PENIRQ?
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Forum Post: AFE4404: Design review
Part Number: AFE4404 Other Parts Discussed in Thread: TPS61041 Tool/software: Hi Ti, Please design review for AFE4404YZP、TPS61041、TPS22916B. Thanks!
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Forum Post: ADS131B02-Q1: Availability of TCR formula.
Part Number: ADS131B02-Q1 Tool/software: Hi expert, I need the TCR formula that represents the temperature coefficient. Please provide it in the form of a polynomial modeling the resistance change with temperature variation.
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Forum Post: ADS8900B: Question about Power supply sequence
Part Number: ADS8900B Tool/software: Hello team, Is there a specific power supply sequence for RVDD, DVDD, REFIN? For example, is it possible to apply DVDD and REFIN first and then RVDD after 10ms? Best Regards, Austin
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Forum Post: RE: ADS114S08B: ADS114S08B noise test issue
Hi team, pls refer customer schematic as attached. thanks e2e.ti.com/.../ADS114S08B.pdf
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Forum Post: ADS125H01: Background to why CRC is implemented
Part Number: ADS125H01 Other Parts Discussed in Thread: ADS125H02 Tool/software: Dear Specialists, My customer is considering ADS125H02 and has a question about CRC. I would be grateful if you could advise. --- I would like to confirm the CRC built into the ADS125H02. More and more recent AD converters have a built-in CRC when communicating via SPI. I think they have provided a mechanism to detect communication errors for safety. Not only the ADS125H02, but recent ADCs appear to attach a CRC to the command when communicating via SPI before sending it. I think they have provided a mechanism to detect communication errors for safety. I would like to know the background to the need for CRC. For example, because errors occur frequently when the SPI speed becomes high, because some industry required the addition of a CRC, etc. --- I appreciate your great help in advance. Best regards, Shinichi
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Forum Post: AFE58JD48: Can I achieve the TGC function using DTGC?
Part Number: AFE58JD48 Other Parts Discussed in Thread: AFE58JD16 Tool/software: I'm currently using the AFE58JD48 to develop an ultrasonic imaging device and I have three questions at present. Firstly, I wonder what the differences are between the DTGC and the ATGC of the AFE58JD48. Can I control the DTGC link via SPI to achieve the TGC (Time Gain Compensation) control for B - mode imaging? Or is it more preferable to use ATGC? Secondly, I've come across some replies on the forum stating that the drawback of the DTGC of AFE58JD48 compared to ATGC is that the adjustment step is 3dB. However, my understanding is that the ATGC control method should also have a minimum step size. Because fundamentally, they both control the quantization switch (the difference being that ATGC uses a field - effect transistor). I would like to ask what the minimum adjustment step of ATGC is. Also, if I use ATGC control, is there a relevant reference routine for FPGA? Finally, I saw in other posts on the forum that AFE58JD16 has a "Digital - Control - Signal - TGC". I'm not certain about the difference in the DTGC function compared to that of AFE58JD48. Thanks and I look forward to your reply.
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Forum Post: RE: ADS1298R: ADS1298R VCM
Hi Ryan, I'm with Jonard and we're supporting a common customer. I have an additional question about the internal RLD summing available on RLD_REF. The difference is that signals for summing is taken after the PGA in ADS1298R, but in ADAS1000, there are taken before the PGA amp. If I understand the derivation depends on the PGA amplifier gain of each channel, where default gain is 6 for the ADS1298R? Currently I am solving the VCM externally using programmable buffers and 10k resistors for creating average from selected input channels. VCM is then put into negative inputs. For this, the VCM could be derived from the same inputs or from different ones for the testing purposes? Kind Regards, Jejomar
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Forum Post: ADC12DJ5200RF: Overrange configuration not saving
Part Number: ADC12DJ5200RF Other Parts Discussed in Thread: ADC08DJ5200RF Tool/software: Hi, We've been using the ADC08DJ5200RF successfully for a while and recently decided to implement an automatic gain adjustment mechanism which uses ORA0 and ORA1 (we're operating in single channel mode). We are setting OVR_CFG during initialisation and following the recommended step order in the datasheet. We're setting the register to 0x0F to enable overrange detection and select maximum pulse duration for the overrange outputs. The issue we're having is it seems like the OVR_CFG register is not holding the value that we're programming into it. Before initially setting it, it seems to have a value of 0x81, and after attempting to write to it, we're reading a value of 0x03. Is there any particular requirement that must be met before this register is set? As mentioned, we're following the exact steps according to the data sheet: 1. Power-up or reset the device. 2. Apply a stable device CLK signal at the desired frequency. 3. Perform a software reset by toggling SOFT_RESET to 1. Wait at least 1 μs before continuing. 4. Program JESD_EN = 0 to stop the JESD204C state machine and allow setting changes. 5. Program CAL_EN = 0 to stop the calibration state machine and allow setting changes. 6. Program the desired JMODE. 7. Program the desired KM1 value. KM1 = K–1. 8. Program SYNC_SEL as needed. Choose SYNCSE or timestamp differential inputs. 9. Configure device calibration settings as desired. Select foreground or background calibration modes and offset calibration as needed. 10. Program CAL_EN = 1 to enable the calibration state machine. 11. Enable overrange via OVR_EN and adjust settings if desired. Adc_SetReg(OVR_CFG, 0x0F); 12. Program JESD_EN = 1 to re-start the JESD204C state machine and allow the link to restart. 13. The JESD204C interface operates in response to the applied SYNC signal from the receiver. 14. Program CAL_SOFT_TRIG = 0. 15. Program CAL_SOFT_TRIG = 1 to initiate a calibration. Before the value is set: Setting the register and reading it back: Thanks in advance, Juan
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Forum Post: RE: VSP5610: Some questions about VSP5610
Is there any progress on the previous issue? thank you.
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Forum Post: ADS1298: Delta-Sigma delay
Part Number: ADS1298 Tool/software: We are currently using an ADS1298 for an EEG application, and we are worried about the delay in the output sampling due to the delta-sigma modulator. How can we estimate it with the configuration registers? Or is it fixed? For example, if we are measuring at 1kbps, what it would be the sampling delay? Kind regards, Ignasi
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Forum Post: ADS1299: SRB1 and SRB2 in standard configuration
Part Number: ADS1299 Tool/software: We intend to use two ADS1299 ICs for ECG and EEG. How can we connect the two devices' SRB1 and SRB2?because we intended to utilize SRB2 as a reference and short all negative pins internally. Is it OK, or do we need to make any changes?
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