Quantcast
Channel: Data converters
Viewing all 88644 articles
Browse latest View live

Forum Post: RE: AFE5803EVM: Companion board

$
0
0
Oh. That does not have jesd interface to use TSW14J50 and unfortunately tsw1400 is obsolete .

Forum Post: RE: ADS8900B: High speed low noise current loop to voltage conversion

$
0
0
Hi Samiha! Here some response of the manufacturer of the SPI to BISS converter chip that we planned to use for this application wrt speed: >> As soon as a BiSS frame is started, our chip will start clocking at the fast sensor interface (max. clock frequency = 20 MHz). >> Your ADC can provide the latest data directly. >> Assuming 24 bit, they can be received by our chip way below 2 us. >> Our chip will then (optionally) calculate a CRC and output the data via BiSS. >> BiSS cycles of 50 us should not be a big deal. >> We have customers who have implemented cycle times < 20 us. So for this chip the 20 kHz loop frequency is not a problem. For the ADC a single channel version is OK because I have to make a few of these converter boxes but each box gets its own PCB with 1 current loop input (4..20mA ). Wrt expected noise I don't know because the current loop is generated by a demodulator module that we buy from a company specialized in these types of measurements and I expect not too noisy at the current loop output. These modules are placed on an DIN rail and our PCB will be also placed into a DIN rail box so the distance wrt cabling will be not too long. Besides we can do some hardware filtering (RC filters) at the input stage where we have to convert the current loop to a voltage matching the input range of the selected ADC. Furthermore I think we have to see in practice how much noise we get and then we can always put some extra filtering in software. I van ask our software team if they can make something that we are able to change the fillering easily during testing. FinalIy I can ask your amplifier team for a good solution for the current loop to voltage conversion when I know the right type of ADC. You suggested a delta sigma ADC for this application. When I look to single channel, SPI ADCs with min100ks/s sampling rate I find : - ADS1271 ( looks more an older Burr Brown type) - ADS127L01 - ADS127L11 - ADS127L21 The final one has the fastest sample rate (and very low gain drift as the ADS127L11) however maybe our SPI frequency of max 20MHz can give some limitations here wrt SPI transfer data rate? How much time will it take from start conversion untill data ready (so the BISS converter can convert the ADC data for these devices (ADS127Lxx) ? Do you think the ADS127L01 would also be sufficient for this? It llos that that one is a little bit accurate? We do not measure absolute positions but a relative displacement and of course we will have some delay between the actual position and the actual data that will be read but that should not be a big deal for us. Which device would you suggest? So I can ask to the Amplifier team for a good solution for the current loop to voltage conversion. And do you have an example schematic that I can use for our PCB so we are sure that everything will work with our design? For the analog power supply we normally get +24V from an external rack supply but these types of supplies will certainly have some times. However nowadays there are DC/DC converters for +24V to +3V3 with very low noise figures. I assume this will be also an important factor here for accuracy? Best Regards Chris

Forum Post: ADC3241: sysref timing

$
0
0
Part Number: ADC3241 Tool/software: We want to use the ADC3241IRGZT in a new system. In addition to a differential CLK input , this also has a differential SYSREF input. For this SYSREF, the data sheet only states that it is used for overall system synchronization. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization.” But what does that look like? There is no timing diagram in the data sheet showing how the SYSREF works. Only table 7.13 contains values. SYSREF and INPUT-CLK seem to play together somehow. Can you obtain more information, e.g. a timing diagram? ciao Hanno (on behalf of my customer)

Forum Post: ADC3683-SP: Hardware Design Files

$
0
0
Part Number: ADC3683-SP Other Parts Discussed in Thread: ADC3683EVMCVAL Tool/software: Hello, We are interesting to implement this ADC in our prototyping board. For that, we need to access of the sources mentioned in the document "SBAU446 EVM User's Guide: ADC3683EVMCVAL". The different links to schematic, pcb and bom of part "5 Hardware Design Files" doesn't work. Could you have an available access ? Thank you in advance. Best regards,

Forum Post: AFE5816: DTGC gain & attenuation setup (AFE5816)

$
0
0
Part Number: AFE5816 Tool/software: Hi, everyone I am using a function generator to create an analog sine waveform, which I input into the AFE5816 and then verify the output through the FPGA. Before inputting the analog signal, I configured the 14-bit serialization, and verified that all test patterns (toggle, sync, ramp) were correctly parallelized and displayed properly on the ILA. However, after inputting the analog signal instead of the test patterns and checking the parallelized data on the FPGA, I observed the following issues: * Analog signal setup : 1MHz 50mVpp sine waveform 1) Low-power mode, DTGC gain code = c0(H) 2) Medium power mode, DTGC gain code = c0(H) 3) Medium power mode, DTGC gain code = 40(H) 4) Medium power mode, DTGC gain code = 40(H), Fixed attenuation -16dB Despite setting the input waveform amplitude and DTGC gain to low values, the peaks of the waveform seem to be clipped. Could you please advise on what might be causing this issue? I thought the issue was due to the signal being too large, so I reduced the analog input signal, but it did not resolve the problem. Although the signal is incomplete, the frequency matched the input in all cases. Thank you,. Sincerely,

Forum Post: RE: DAC8742HEVM: Sending data via UART IN pin on DAC8742HEVM

$
0
0
Ibrahim, How is this different than your other post? For reference, see the link below. https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1342993/dac8742h-uart-communication-in-dac8742hevm In that setup, the GUI send the UART_IN signal, it translates it to the PAFF signal and then the GUI receives it on UART_OUT. Are you sending a different UART_IN signal? If you're trying to duplicate this, maybe start by duplicating the settings and the data. I don't think you would need the FULL DUPLEX setting again, but just in case, click that. Then duplicate the data. Send what I sent on the last post of 0x91 0x00 0xAE 0x05 0x07, and then generate the read for two bytes. This is how it was set the last time. I would imagine that would work as long as the EVM board is configured the way it was configured in the last post. Joseph Wu

Forum Post: ADC12DL040: Does TI have similar spec like AD9231?

$
0
0
Part Number: ADC12DL040 Other Parts Discussed in Thread: ADC12D040 , Tool/software: Hi team, Does TI have similar specs like AD9231? ADC12DL040 or ADC12D040? But INL and DNL are worse than ADC12D040. Do you have a better solution? thanks

Forum Post: ADS124S08: BOCS switched off while converting?

$
0
0
Part Number: ADS124S08 Tool/software: I use BOCS to detect broken sensors and observe unexpected behavior. I proceed as follows: (very simplified example) while(1){ INPMUX to Ch0(+) / Ch1(-) // set channel System Control Register = 0b11110000 (BOCS = 10uA) // switch on BOCS start_ADC() // start acquisition while (not(DRDY)){} // takes about 100ms read_out_ADC() System Control Register = 0b00010000 // switch off BOCS } But the inputs are not pulled to VDD and VSS. But if I set a delay before the acquisition, it works: while(1){ INPMUX to Ch0(+) / Ch1(-) // set channel System Control Register = 0b11110000 (BOCS = 10uA) // switch on BOCS start_ADC() // start acquisition while (not(DRDY)){} // takes about 100ms read_out_ADC() System Control Register = 0b00010000 // switch off BOCS } This gives me the impression that BOCS is disconnected from the MUX (AIN0 and AIN2) during the acquisition. Can you confirm this? I have a 100nF CAP capacitance between AIN0 and AIN1. I would expect this to charge up within the loop and maintain the voltage, even without the delay(5ms) before start_ADC(). But the longer the delay, the faster the CAP charges

Forum Post: ADS7044: Data output vs Acquisition

$
0
0
Part Number: ADS7044 Other Parts Discussed in Thread: ADS7054 Tool/software: Hello support, I am working on two projects using ADS70xx family. - project 1: using ADS7044 (12 bits) - project 2: using ADS7054 (14 bits) I would like to clarify what is the data output when performing a single cycle, because this is explained differaly between the two datasheet: ADS7044: ADS7054: Can you confirm whether the data output during cycle N for ads7044 is the data from sample N, and whether the data output during cycle A for ads7054 is the data from the previous sample (A-1) ? If this is the case, it means that both device works differently: for the ads7044, the latest data can be obtained by running only one cycle. for the ads7054, the latest data can be obtained by running two cycles: the first for acquisition and the second for sending the data. thank you,

Forum Post: RE: AFE5816: DTGC gain & attenuation setup (AFE5816)

$
0
0
Hi, It is not data saturation issue . ADC data coming out in twos complement format . Because of this you are getting this kind of waveform . 1) Change your fpga code to change this twos complement format from device to normal format 2) In the device there is option to change output format . You need to write register 4 , bit 3 to 1. (0x8 is what you need to write to enable this bit)

Forum Post: RE: AFE5816: DTGC gain & attenuation setup (AFE5816)

$
0
0
Thank you. But, In datasheet there is a comment that I must write 0 in register 4, bit 3 Is that OK?? Additionally, can you give me some example that change twos complement format to normal format?? I've never made that kind of VHDL codes . Thank you

Forum Post: RE: AFE5816: DTGC gain & attenuation setup (AFE5816)

$
0
0
Yes . That is ok . You can change that . You can search online for twos complement to offset binary conversion . Attaching some example page which explains this. https://en.wikipedia.org/wiki/Offset_binary

Forum Post: DAC80508: can it support both 12bit and 16bit

$
0
0
Part Number: DAC80508 Tool/software: Customer would like to check whether they can use DAC80508 for both 12bit and 16bit applications, to achieve compactible design. If they want to use 12bit configuration, is high 12bit effective or low 12bit effective for the data input D[15:0]? Could you please help check it? Thank you.

Forum Post: RE: TSC2007: Touch Screen Drivers Interface Y+/Y- cannot work

Forum Post: RE: ADS54J60: ADS54J60

$
0
0
Hi Rob, we are downloaded again IBIS model and simulated. Still we are facing simulation error, please find the below error snapshoot. Tool Name: Mentor Graphics (Hyperlynx) Ver: VX2.10 Regards, Nanjegowda

Forum Post: RE: DAC8742HEVM: Sending data via UART IN pin on DAC8742HEVM

$
0
0
Dear Joseph, Thank you for your response. Correct, last time I try send PAFF UART data on the GUI Software. Now I still can send and receive the data on GUI. But when I try to send that data 0xEA 0x91 0x00 0xAE 0x05 0x07 through UART_IN pin (not via DAC8742 GUI Software), I didn't receive the data. I use USB to serial converter on my PC to send the data. Here is wiring configuration: Green ==> GND to GND pin USB Serial converter Orange ==> UART_IN to TX pin USB Serial converter Blue ==> UART_OUT to RX pin USB Serial converter I send the same UART data through UART_IN pin via HTerm software (Baudrate 57600, 8N1). After I send the data via HTerm software (not via click "Generate Write" button on DAC8742 GUI software) and I try to receive the data by click the "Generate Read" button on DAC8742 GUI Software, I didn't get anything. Could you give me some advise about this? Thank you for your support. Regards, Ibrahim

Forum Post: RE: TX7332: TX7332 output pattern and power capabilities

$
0
0
Hi, Please find my reply below for your questions: Even though the device has multiple pattern profiles, the selection of a pattern profile for transmit is common for a group of 16 channels (1-16 or 17 to 32). To calculate this, you can refer to the section "Thermal Information" in the datasheet, where we have provided the thermal resistance of the device, in degC/W. This is around 20.8C/W. This means that for every 1W of power dissipation, the average device temperature increases by ~20.8C. The device shutdown temperature is ~110degC. Based on the above 2 numbers, you can calculate the maximum average power dissipation possible, without the device going to shutdown. If the system has an ambient temperature of 30C, the maximum possible increase in temperature is 80C, without triggering shutdown. This translates to ~3.85W. Yes, low frequency pattern can be programmed to the device. Thanks and Regards Savyan

Forum Post: RE: TX75E16EVM: TX75E16EVM GUI Device Cannot be Found

$
0
0
Hi Zhong, My apologies for the delay in response. Were you able to get the problem resolved? If not, could you please drop a mail to support_us_afe_tx@list.ti.com to get assistance for the problem, as this device is covered under NDA? Thanks and Regards Savyan

Forum Post: RE: AFE5851EVM: What is required alongside this part? (ADSDeSER-50EVM or TSW1400EVM)? Are there updated versions?

$
0
0
Hi, Unfortunately both capture cards are obsolete. Currently there is no other capture card. I would like to ask what do you want to test on EVM ?

Forum Post: RE: ADS122C04EVM: Reading temperature and connecting a wheatstone bridge

$
0
0
Hello, I was able to get the temperature sensor working by correctly writing to the registery. It now reads and calculated temperature accurately. Now I am struggling with the strain-gauge bridge. I have connected by brige up as per instruction in figure 20 (in the EK) . I used the bridge with another chip and it worked then. I have set up the registery according to figure table 10 (in the EK) and chapter 8.6 in the specifications. This is is how I set the registery (confirmed on the scope). Register 0x00: 0x4F (01001111) Register 0x01: 0x0E (00001110) Register 0x02: 0x80 (10000000) Register 0x03: 0x00 (00000000) I seem to be getting just random data: ADS122C04 Raw Data: 00000000 00000000 00100111 ADS122C04 Raw Data: 00000000 00000000 01011000 ADS122C04 Raw Data: 00000000 00000000 00101110 ADS122C04 Raw Data: 00000000 00000000 01001000 ADS122C04 Raw Data: 00000000 00000000 00011010 ADS122C04 Raw Data: 00000000 00000000 01011111 ADS122C04 Raw Data: 00000000 00000000 00111111 Are my registery settings correct? Are there any other changes on the EK I need to make?
Viewing all 88644 articles
Browse latest View live


<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>