Hi Miguel, It's starting to look like the TI-JESD204-IP is being end of lifed as there have been multiple missed dates given for the newer release and with multiple reasons given, but with the bottom line that they never actually supported Vivado 2023 when it was current: Just under a year ago in 3Q2023 it was stated that Xilinx had changed the IP block encryption/decryption flow and broken the TI IP in the process: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1260281/ti204c-ip-compatibility-with-vivado-2023-1 At the end of 2023 it was stated that the next release would support the vivado block design implemention flow, and that it was expected for January 2024 2024: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1299136/ti-jesd204-ip-how-to-use-ti-204c-ip-on-vivado-block-design?tisearch=e2e-sitesearch&keymatch=JESD204%252520Vivado Here it was stated that it was delayed to February 2024: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1316519/ti-jesd204-ip-ti-jesd204-ip-next-release And since then similar questions have received no answers including this one 4 months ago: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1338678/adc12qj1600evm-is-ti-jesd204-ip-for-vivado-2023-x-available Basically they've taken so long to support Vivado 2023 that now Vivado 2024.1 is out for 2 months (30 May 2024). While you might come to different conclusions, I'm starting to plan to purchase the Xilinx IP as the TI IP doesn't look like it can be depended on for future designs.
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Forum Post: RE: TI-JESD204-IP: Support for Vivado 2023.x
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Forum Post: ADS8588S: Questions about Read after conversion
Part Number: ADS8588S Other Parts Discussed in Thread: ADS8584S , Tool/software: Dear Technical Support Team, I have questions about ADS8588S and ADS8584S. Q1 The ADS8588S is equipped with an 8-channel ADC, but when reading only 4 channels (ch1 to ch4) in Read After Conversion, assert only “CONVSTA” to '1' and use “Figure 2. Data Read Operation Timing Diagram” and ‘Figure 4: Parallel Data Read Operation, CS and RD Separate’. (CONVSTB is fixed at '0' and not used) Is it correct? Q2 If I read only 4 channels with Q10, will the tCONV (Conversion Time) of ADS8588 take 3.7 to 3.9us? Since tCONV of ADS8584 was 2us (Typ), I was wondering if it can be shortened. Q3 If the ADS8588S installed in the ADS8588SEVM-PDK is replaced with the ADS8584S, is there any problem other than a decrease from 8 to 4 channels? For example, is there any change in the pin assignment of the J9 connector pins on the board, or are there any pins that can no longer be used? Best Regards, ttd
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Forum Post: AMC1210MB-EVM: Connection Issue Due to Erased Firmware
Part Number: AMC1210MB-EVM Other Parts Discussed in Thread: AMC1210 , Tool/software: Dear TI Support Team, My company recently purchased the AMC1210 IC and we are encountering difficulties in making it function properly in our design. To ensure the AMC1210 is suitable for our needs, we acquired the AMC1210MB-EVM evaluation board to test the IC on reliable and trusted hardware. Unfortunately, an error was made: without considering the consequences, I erased the flash memory of the LM3S3738 MCU on the evaluation board, intending to develop on this MCU. As a result, I am now unable to connect to the AMC1210EVM software, as the appropriate firmware is no longer running. Could you please provide the firmware for the AMC1210MB-EVM or direct me to a source where I can obtain it? Thank you for your assistance.
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Forum Post: RE: AFE159RP4: RTM
Hi, Do you have any update? Best Regards, Nishie
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Forum Post: RE: DAC39RF12: Regarding the compatible xilinx evaluation board for DAC39RF12 in terms of TI Based JESD IP core and secure folder access
Hello support team, Kindly provide the above details as soon as possible, as our finalization of FPGA will be based on your response.
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Forum Post: RE: ADS124S08: Data received always 0 value
Yes. After changing gain , My issue got resolved. Thank you very much
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Forum Post: RE: ADS1115: ADS1115 3 out of 4 channels steady readings but the 4th has too much noise
Hi Angel My loop sequence is : Send 0x83C3 // specifies the setting and starts a read Send 0x00 // This I am told specifies the data format ( I have tried without this and it seems to make no difference ) Wait 20ms // for ADC to convert a reading. Read from ADS1115 and save to channle 0 data This repeats using 0x83C3 / 0x83D3 / 0x83E3 /0x83F3 for channle 0, 1, 2 and 3 This then loops back and starts again. The noise across all channels was a code problem that I think has been solved as it is not coming up anymore. But when I read from channel 0 ( or any single channel ) continuesly and do not change the Mux, the readings are stable, only when I start changing signals around does it come up with the first repeat of the loop. I ended up reading from channel 0 twice and throwing away the first value, this give me a much cleaner reading, I still do not know why though.
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Forum Post: RE: ADS42LB69: Dithering control with a hidden register bit
Hello Rob, Thank you for the answer. I can only regret it. Having access to the on chip DAC used for dithering could be a useful function for advanced users. Best regards, Jean-Luc
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Forum Post: ADS8167: ADS8167 could not communicate with SPI
Part Number: ADS8167 Tool/software: Hello, The command we use to start the Auto sequence mode on the ADS8167 integrated circuit is 0x1EU, which is the response we get. We cannot read the ADC data we need to read. Is there a status register that we can communicate with to understand whether all the channels in the integrated circuit are working? Best regards,
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Forum Post: DAC902: Is this the best alternative to the AD9706?
Part Number: DAC902 Tool/software: Hi TIer My customer have a ultrasound application which use AD9706 in TGC module. They need some low cost chip in this project . I search in TI.com and found AD9706. However, I see DAC902 is old. Do you have some suggestion about it? Thank you very much.
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Forum Post: ADC3664: Reduce clock pin
Part Number: ADC3664 Tool/software: Dear Technical Support Team, I'd like to use six ADC3664 on the same board and it has four clks. Do you have any idea to reduce or sharing clocks? CLK (in ) DCLKIN(in) DCLK(out) FCLK(out) According to previous post, it seems to reduce and sharing clocks. Is it correct? https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1388138/adc3664-sharing-dclk-fclk?tisearch=e2e-quicksearch&keymatch=ADC3664 https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1173059/adc3663-clock-inputs-for-sample-clock-clk-dclkin?tisearch=e2e-sitesearch&keymatch=ADC3663%20DCLKIN# Best Regards, ttd
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Forum Post: RE: ADS1263: Do we have any software example to calculate current using ADS1263 in diff end mode ?
Hi Bryan, Yes, This is the new behavior I found from ADS1263. I measured the voltage between AIN0 - AVDD is 2.405 v & AIN1 - AVSS is 2.554 v
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Forum Post: RE: ADS8588S: Questions about Read after conversion
Hi Tom, The background of my question is that I want to process 1 sample minute (200Ksps) of data from a sensor within 5us inside FPGA. Since the ADS8588's conversion time accounts for about 4us of the 5us processing time, we would like to replace it with the ADS8584 to shorten the conversion time to 2us (Typ). The Conversion Time of ADS8588 with EVM is as long as 3.9us, so we were looking for a way to shorten it by 200ksps, however from your answer, I recognized that there is no way to shorten it. If you have any advice on the above, please let me know. Best Regards, ttd
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Forum Post: ADC12DJ3200: Bias of a certain period
Part Number: ADC12DJ3200 Tool/software: Dear Technical Support Team, When I checked the operation of this ADC, I input a synthesizer (sine wave), As shown in the attached graph ③, there is a bias of a certain period of about 18 cycles for the resolution of 12-bit ADC. I connected this synthesizer to another measuring instrument (oscilloscope), but this symptom did not occur. Is there any cause of this symptom or any register that can correct it? For reference (See attached file) e2e.ti.com/.../ADC12DJ3200.pdf ① sine wave obtained by ADC12DJ3200 ② histogram of ①. ③ histogram of ② with the area around 2048 enlarged Best Regards, ttd
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Forum Post: ADS9813: About the release date
Part Number: ADS9813 Tool/software: Hi team, When is the mass production release timing for this device? Regards, Ryu.
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Forum Post: RE: DAC7612: Replacement DAC7621
Hi Katlynne, i am logged in but all of those components are listed out of stock... All the best Markus
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Forum Post: RE: ADS125H02: For Vrms at 40ksps
Hi Bryan, The register settings are as follows [ADS125H02 Register Settings] ID 61 STATUS0 01 MODE0 80 MODE1 00 MODE2 00 MODE3 00 REF 0A OFCAL0 00 OFCAL1 00 OFCAL2 00 FSCAL0 00 FSCAL1 00 FSCAL2 40 IMUX FF IMAG 00 RESERVED 00 MODE4 5B STATUS1 00 STATUS2 01 Regards, Ryu.
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Forum Post: RE: ADS1261: IC being non-responsive some times after some time
Hi Bryan, There is a complete communication breakdown and soft RESET command does not help, a power cycle is required to recover. Thanks - Samyak
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Forum Post: RE: ADC3444: Reference design/source code for SPI Controller
Hi Chqase, Thank you for sharing the source files, but they're not helpful. Regards, Satham
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Forum Post: DAC34SH84: Reference design
Part Number: DAC34SH84 Tool/software: Hi supporting team, We are planning to use the DAC34SH84 device in our project. Could I please get a reference design/source code for SPI controller? Regards, Satham
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