Hi Dmitriy, Unfortunately, we cannot support this older version, as we don't know either and this SW was developed by a third party vendor that we no longer work with. I see on the other E2E post you are looking at JMODE5. Is that correct? We are here to support you, but we cannot use older outdated HW and SW. We will set you up with newer tools. Should I close this post and we continue on that one? Please advise. Regards, Rob
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Forum Post: RE: TSW14J57EVM: PC doesn't recognize
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Forum Post: RE: ADS7049-Q1: 4-wire SPI
Doing well Brian, The ADS7049-Q1 has no need for SDI. Since there is no need for SDI, you only need 3-wires for control. What is the ASIC trying to write too? Send me a note with more details please.
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Forum Post: RE: ADS1292: ADS1292 application circuit review request and related inquiries
Hi, Ryan The customer has requested privacy, so I will respond via email.
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Forum Post: RE: DAC82001: Small form factor DAC with 6V supply?
Hello Katlynne-san, I confirmed there is also 5V supply we can use. I close this post. Thank you for recommendation. Best regards,
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Forum Post: RE: ADS1220: Measure of RTD Pt100 with ADS1220 and STM32H7 (over SPI connexion)
Dear Angel, more updates as we progress but not yet at perfect output_code accuracy that the ads1220 is able to deliver. After some bitshifting fixes we now have an output code in average of 0x21A70 (78.87ohms) over few ms sampling averaging but the pt100 connected (using a Yokogawa CA150 to output perfect 100ohms) with 100ohms RTD value. So we have delta of about 20ohms somewhere. Does it ring a bell for you somewhere ? I recall our configuration below ADS1220_CONFIG0_PGA_ENABLE | ADS1220_CONFIG0_GAIN_1 | ADS1220_CONFIG0_MUX_AIN1_AIN0; ADS1220_CONFIG1_BCS_OFF | ADS1220_CONFIG1_TS_DISABLED | ADS1220_CONFIG1_CM_CONTINUOUS |ADS1220_CONFIG1_MODE_NORMAL | ADS1220_CONFIG1_DR_20_SPS; ADS1220_CONFIG2_IDAC_250UA | ADS1220_CONFIG2_PSW_OPEN | ADS1220_CONFIG2_FILTER_BOTH | ADS1220_CONFIG2_VREF_EXTERNAL0; ADS1220_CONFIG3_DRDYM_ONLY_DRDY | ADS1220_CONFIG3_I1MUX_AIN2 | ADS1220_CONFIG3_I2MUX_AIN3; I wish I can finalize this correction soon to be able to make accurate tests of 8 ads1220 in parallels. Much regards, Zabieru.
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Forum Post: AFE4500: AFE4500
Part Number: AFE4500 Tool/software: TI Team: 1) Highest sampling frequency in AFE4500 if we have to measure both ECG and Bioimpedance simultaneously and plot the signal graphs simultaneously. 2) Does the 4960 AFE have an internal mixer and does it need any settling time? Our goal is to measure ECG and bioimpedance signals as fast as possible. 3) Can we use the calibration resistor as 2nd AFE if it is accessible to us? 4) Do we need to measure PTT (Pulse Transit Time) by using two BioZ AFEs or is it possible to achieve this by using just one AFE by measuring the delta Z across two sets voltage sensing electrodes at two different time intervals? Regards Sudarshan
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Forum Post: ADS8860EVM-PDK: compatibility with EVAL-ADXL100X accelerometer
Part Number: ADS8860EVM-PDK Tool/software: Hi Team, Good day. I am posting this inquiry on behalf of the customer. I have an accelerometer that requires an ADC that can help to digitize the data. I was wondering if the ADS8860EVM-PDK is compatible with my accelerometer and was hoping if you could help to clarify this matter. Specifications of the Accelerometer: Model Number: EVAL-ADXL1001 Manufacturer: Analog Devices ODR: 9.5kHz resolution: 16 bits I would appreciate it if you could inform me of the following: 1. Is the ADS8860EVM-PDK compatible with the proposed accelerometer? 2. Are there other components that I will need other than the ADS8860EVM-PDK? Thank you for your help. Kind regards, Marvin
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Forum Post: RE: ADS7049-Q1: 4-wire SPI
Hello Tom, Customer mentioned in the Encoder system, there're two devices using 4-wire SPI comm with ASIC. One is angle sensor MT6835, the other one is ADS794x(for example). The SDI function is needed to handshaking which data in the Sensor or ADC is needed for ASIC. Is it making sense? Is there low-cost 4-wire ADC with the sample requirements you recommended? ASIC SPI pinout: Angle Sensor: 4-Wire SPI Regards Brian
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Forum Post: RE: ADS1220: use without DRDY pin on SPI comminicaiton
Okay Henry thank you so much, i will be waiting your answer
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Forum Post: RE: DAC80502: The error difference between REF5050 and internal REF
Hi Takumi, The error directly translates to DAC error. If the reference is 0.05% off, the DAC output will be 0.05% off. If the reference is 0.1% off, the DAC output will be 0.1% off. The different value does not have much of an effect. If you use the 5V reference, you will need to use the internal reference divider and then the internal buffer gain to get a 5V output. If you use the 2.5V reference, you will need to use the internal buffer gain to get a 5V output. Both references will functionally behave the same if you configure the internal settings as I've mentioned above. Best, Katlynne Jones
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Forum Post: RE: DAC38J84: Can 1 or 2 lanes be used without interpolation?
Hi Matthew, Thanks for the clarification. For now, I'll plan on using 4 lanes per device.
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Forum Post: RE: ADS8556: ADS8556 Capacitor Values with DC BIAS - AVCC and REFC_x pins
Hi David, You should be okay to use those larger valued capacitors, but the device start-up time may increase slightly. Please place them close to the device as noted in the datasheet. Best regards, Samiha
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Forum Post: RE: DAC80502: How to calculate TUE?
Hi Takumi, TUE stands for total unadjusted error. Typically this will include all DAC errors. The value in the datasheet is a measured value (including offset error, gain error, and INL) which is better than a calculated value because the calculated value is a very conservative value. W e usually don't see devices with most extreme gain error, offset error, and INL at the same time, but the calculated TUE uses these worst case values. The equations on page 35 are showing how to include the drift values and reference error to the measured TUE. You are correct 0.112%FSR(before calibration) is from "equation 2" and 0.05%FSR(after calibration) is from "equation 5". For the calculation, follow equation 2. Use the TUE spec from the electrical characteristics table. This spec was measured at one temperature, so equation 2 is adding the effects of the drift and reference. The drift specs in the datasheet are given in unit/C, so you would multiply by your temperature range to know the effect of the drift. In the datasheet example they used 0 to 100C. Before the calculation, all of the errors should be converted to the same units. Either LSB, or %FSR. This is what is shown in equations 3 & 4 Best, Katlynne Jones
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Forum Post: RE: DAC38J84: Can 1 or 2 lanes be used without interpolation?
No problem Greg. These devices are quite particular about these types of things. I'm just curious, can you not use interpolation due to the interpolation filter bandwidth?
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Forum Post: RE: ADS1298ECGFE-PDK: ADS1298ECGFE-PDK GUI
Hi Nivethitha - can you share the complete register settings? Also, can you try an alternate signal source? You can configure the inputs to measure an internal square wave test signal, or connect a function generator with a 100 mVp sine wave. Regards, Ryan
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Forum Post: RE: DAC38J84: Can 1 or 2 lanes be used without interpolation?
It's more that my application is a bit unconventional, and I care more about minimizing settling time of the DAC outputs than a clean frequency response. I won't even be using a reconstruction filter of any kind, and just using the unfiltered zero-order-hold behavior of the DAC. Enabling interpolation would cause long ringing transients after a step change in the signal, which would be very detrimental in my use case.
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Forum Post: RE: TSW14J57EVM: TSW14J57revE_BRAM_RxOnly_16L_FIRMWARE Download
Hi Ryan, Unfortunately, the FPGA design used on the TSW14J57EVM was developed through a third party and is available only as a bitfile (source code cannot be shared). In addition, it contains a Xilinx JESD IP, which needs to be licensed directly from Xilinx. If you are looking to create a JESD based FPGA design and your target is a Xilinx FPGA, kindly requisition the TI JESD IP from the following link: https://www.ti.com/tool/TI-JESD204-IP The JESD IP archive contains a number of generic reference designs that you can use as a starting point and then customize for your specific link parameters. Regards, Ameet
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Forum Post: ADS8681: RVS not going high after reset
Part Number: ADS8681 Tool/software: This is my first use of the device. All grounds are connected to the same return plane. Upon initial power-up or reset (RST_n pin driven to 3.3V), the RVS pin remains low. According to section 7.4.2.1 of the datasheet: "In order to exit any of the RESET states, the RST pin must be pulled high with CONVST/CS and SCLK held low. After a delay of tD_RST_POR or tD_RST_APP, the device enters ACQ state and the RVS pin goes high." I read this to mean that CONVST/CS should remain low, along with SCLK until RVS goes high. Please advise. Please advise. I am driving the device with an FPGA using 3.3V I/O. DGND = 0V AVDD = 5.2V AGND = 0V REFIO = ~4.09V REFGND = 0V REFCAP = ~4.09V AIN_P = Unconnected AIN_GND = 0V RST_n = 0V or 3.3V SDI = 0V CONVST/CS_n = 0V (FPGA is waiting for RVS to go high before starting a conversion) SCLK = 0V SDO-0 = 0V when RST_n = 0V; 3.3V when RST_N = 3.3V ALARM/SDO-1/GPO = 0V RVS = 0V DVDD = 3.3V
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Forum Post: RE: ADS127L11: Antialiasing and Digital Filters
Hello Jonas, It depends on the expected frequency content of the signal and the type of digital filter that you are using. In your case, you will not have any degradation in performance. If you are using a low-latency SINC filter, then the attenuation at f-DATA/2 (Nyquist) is not all that great (SINC4 has -15dB of attenuation at f-DATA/2). In this case, you may want to use an analog anti-alias filter at a lower f-3dB frequency to further attenuate aliased signals to an acceptable level. If you increase the OSR, you also reduce the f-DATA/2 alias frequency, in which case the external anti-alias filter will not provide as much attenuation benefit. However, in the case of the wideband filter, the filter will provide very good attenuation for any frequency greater than f-DATA/2 up to near the modulator frequency. In this case, increasing the OSR will not have any negative effects for aliased signals. The AAF is still needed at the modulator frequency, but since this does not change for different OSR's, you will still get the same attenuation. In fact, the analog filter is usually set higher than the digital filter f-3dB point when using a wideband filter to reduce the effects of the analog filter in the digital filter passband. The example anti-alias filter design in the ADS127L11 datasheet configures the digital filter to 400ksps, with an f-3dB frequency of 175kHz, but the analog filter is set to 500kHz to keep near 0dB in the digital filter passband. Regards, Keith Nicholas Precision ADC Applications
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Forum Post: RE: ADS1282: Noise Floor is too large
Hi Keith, Thank you again for detailed reply. I have modify the code to accomplish 24 bit and 100 nS delay between filing edge of ADC RDY and rise of SCK. Please see scope plots below and comment. To do ADC counts to volts conversation I am using follow formula: = 0.5 * 5V / (2^23 - 1) * , I am assuming MSB is sign bit. Please advise if this formula making sense. Thank you for your support. Iouri
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