Hello Kevin, It appears a solution did not happen in that week. I don't expect an answer anytime soon. Do you have an older version to use? I apologize for the delay and difficulties.
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Forum Post: RE: ANALOG-ENGINEER-CALC: ANALOG-ENGINEER-CALC Version 1.71 Blocked by Windows Defender
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Forum Post: RE: TSW14J57EVM: PC doesn't recognize
Hi Dmitriy, Please install ver 5.2 as Kyle suggested above. Not sure about the admin credentials for this version. Regards, Rob
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Forum Post: ADS54J60: No K-Symbols during the CGS stage
Part Number: ADS54J60 Tool/software: Hello, We don't see K-symbols in CGS stage in JESD, only random data on the transceivers. The SYNC signal is low as was observed on ADC side. Do we need any specific settings for the ADC to force the ADC to send K-Symbols in the CGS stage? I am adding a file that shows what we are writing to the ADC over SPI. Any help is greatly appreciated! Thanks, Ryan ADC_config
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Forum Post: RE: ADS54J60: No K-Symbols during the CGS stage
For reference this is what we see in the Vivado HW debugger
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Forum Post: RE: ADS124S08: PT1000 design requirements and selection of passive parts
Hi Gopika Raj V S, Based on the connector, I will assume that this is a 4-wire RTD configuration. The analog input filter configurations should be fine, but there are a couple of considerations. If you desire to use any PGA gain beyond a gain of 1 you will need to increase the value of the R138 reference resistor. There is a trade-off in doing this as you will need to decrease the IDAC current you intend to use so that you do not go beyond the compliance voltage. The means that the total voltage drop of the current path must be less than the specified compliance voltage as listed in the electrical specifications in the datasheet ((AVDD - AVSS) - 0.6V or (AVDD - AVSS) - 0.4V depending on IDAC current setting). More importantly, you have no input protection for the current source coming from AIN0. Any transient must be limited to +/-10mA maximum through the AIN0 pin. You could add a series resistor to limit the current, but you will need to make sure the IDAC compliance voltage is being met. Another option would be to add a series Schottky diode. However, a diode will only limit current in one direction. There are a couple of useful resources. One is A Basic Guide to RTD Measurements and the other is an RTD calculator tool . Best regards, Bob B
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Forum Post: RE: DAC7731: S/O: 218291
Hi Kent, That date code is mid-2023 so it would be affected by the PCN. Thanks, Lucas
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Forum Post: RE: TSW14J57EVM: PC doesn't recognize
Hi Dmitriy, It just occurred to me that you are trying to use an older J57, REVB. This is no longer supported and hasn't been for some time. The other issue, is that the J57 EVM is obsolete due to the FPGA being obsolete. Lets start by understanding what Jmode and/or features you are trying to evaluate with the ADC12DJ3200? Thanks, Rob
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Forum Post: RE: TSW14J57EVM: PC doesn't recognize
Hi Rob. I've created a dedicated thread to get help on the configuration of the capture board for our specific mode. Shall we continue there? As for this thread, I understand the problems with the hardware. What I didn't understand is why, after admin permission was required to install the software, Windows continues to ask me to enter the credentials to simply run the software. This renders it useless if you don't and can't get admin rights on a PC.
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Forum Post: RE: ADC12DJ5200RFEVM: Diagrams in ADCxxDJxx00RF Evaluation Module User's Guide
Hello Makoto, Yes the diagram looks fine, I am still trying to understand exactly what features you are looking for? Is the requirement just on board clocking of the ADC or something more complicated? Thanks, Eric
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Forum Post: ADS1298: Strange volatege on vcap and vrefp
Part Number: ADS1298 Tool/software: Hello Team, Posting on behalf of my customer: I have a problem with ads1298 with strange voltages on VCAPS and VREFP. On every VDD, VSS pin I have correct voltage AVDD: 2.5V ,AVSS:-2.5V and DVDD: 3.3V. In VCAP1 I have -1.2V instead of 1.2V. on VCAP4 and VREFP i have -2.5V, VCAP2 is 0V and VCAP3 have corrent 4.3V. I think because of that my spi don't work well. 1.SCLK 2.CS 3.MISO 4.MOSI schematic below Thanks in advance. Regards, Renan
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Forum Post: ADS54J60: JESD K symbol not present during CGS initialization
Part Number: ADS54J60 Tool/software: Hello TI support, We have been facing thjis issue for a while now. We need to deliver to our customer ASAP and my colleague Ryan Carpenter has posted detailed question here: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1368138/ads54j60-no-k-symbols-during-the-cgs-stage Can someone help us out please? Rgds Nory cell: 7757718527
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Forum Post: RE: ADS1298: Strange volatege on vcap and vrefp
Thanks, Renan. Are these voltages measured with respect to GND or AVSS? Our typical device specs are measured with respect to AVSS , but it looks like the customer is measuring with respect to GND. If that's true, then VCAP2 and VCAP3 are both ok. VCAP1 is the internal bandgap voltage used to derive the internal reference (VREF). VCAP1 should measure 1.2 V after power-up, while VCAP4 should measure 600 mV (VREF / 2). The ADS1298 uses SPI Mode 01 (CPOL = 0, CPHA = 1). SCLK should idle low between frames. Do you see the nDRDY pin toggling after startup? Are you following the initialization procedure in section 10.1.1? Regards, Ryan
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Forum Post: RE: DAC43401-Q1: Want to know the right register for my situation
Hi Jaesong, No, that is not correct. I am using the following sequence with no load connected to the output (only the scope), and I see a square wave output with a high output of ~1.16V and low output of ~0V. 0xD3 0x5208 0x25 0x0A58 0x26 0x0000 0xD1 0xC104 0xD3 0x0108 My scope is connected directly to the output pin, which is shorted to the FB pin. 1.16V is expected with margin high data of 0x0A58. 0x0A58 corresponds to 10-bit data of 662 in decimal based on how the data is aligned in the register: Frequency is ~306Hz which is expected based on the datasheet equation: For the second question, to configure more output frequencies, you will need to disconnect the VOUT pin from the FB pin. Configure the desired frequency using triangle or sawtooth waveform mode using the below equations. The duty cycle is configured with the FB pin. Set the FB pin to VREF x gain x 0.5 for a 50% duty cycle. The drawback is that the square wave output of this mode is always 0V to VDD. Best, Katlynne Jones
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Forum Post: RE: BP-DAC11001EVM: Software cannot connect to DAC
Hi Adarsh, Akhilesh will provide some suggested next steps for this issue. Best, Katlynne Jones
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Forum Post: RE: ADS54J40: Inquiry on how to calculate overall latency of ADS54J40
Hi Kilyong, Thank you for the configuration info. I will realy this to the team and get back to you with the delay. Best, Luke Allen
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Forum Post: AFE4432: what is VHR
Part Number: AFE4432 Tool/software: The datasheet for AFE4432 mentions voltage headroom (VHR), but I can't understand what this mean. Does this mean the minimum voltage required for the TXN pin? For example, if used with TX_sup=3V and VHR=1V, does that mean that the LED voltage drop must be 2V or less?
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Forum Post: RE: ADC12DJ5200RF: JESD pattern maximum length
Hi Geoff, Please refer below. 1. Data rate : 6Gbps-10Gbps 2. Board material : Megtron 6 3. Traces : Stripeline Thanks.
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Forum Post: RE: ADS1278: Figure 88; What is the purpose of the flip flop?
Hello Rahul, Welcome to the TI E2E community. The flip-flop is included in order to meet the timing requirements of some MCU/DSPs. The limitation is the SCLK prop delay t-DOPD. If you use CLK=27MHz and SCLK=13.5MHz , then you will not need this flip-flop. The ADS1278 launches data on the SCLK falling edge, and the host MCU will normally capture data on the SCLK rising edge. As long as the prop delay is less than 1/2*t-SCLK, then you will meet the timing requirements. Assuming IOVDD is less than 3.15V, then the maximum t-DOPD is 32ns. This will limit the maximum SCLK frequency to 15.6MHz. Take a look at this e2e post that describes this in more detail: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/676351/ads1278-tdm-mode-sample-rate-limitation You can also configure your SPI port to capture data on the falling edge of SCLK. In this case, the minimum hold time will be 10ns. This mode will allow a maximum SCLK of 27MHz without the use of a flip-flop. Regards, Keith Nicholas Precision ADC Applications
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Forum Post: RE: ADC12DJ5200RFEVM: Diagrams in ADCxxDJxx00RF Evaluation Module User's Guide
I would like to use both the Onboard Clocking System (which generates the input clock from the LMK61E2) and the External Reference Clocking System (which uses an external clock). I want to change the clock source statically using JumperPin. (Not dynamic.) As I asked in Q2 to Q4, ADC EVM User Guide describes different SYNC and SYSREFREQ paths for each Clocking System, so I don't know how to design my system where both onboard and external reference clocking system coexist (especially a clock system using LMK and LMX).
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Forum Post: RE: ADS7049-Q1: 4-wire SPI
Hello Tom, Long time no see. Hope you're doing well. Since Encoder is using ASIC to do the magnetic signal converter and other functions, ASIC is only supporting 4-wire SPI interface. is that making sense? Regards Brian
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