Hi d.gre, Our engineer that supports the ADS1220 is out of the office today, so we will respond to you later this week. Thanks for your patience -Bryan
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Forum Post: RE: ADS1220: use without DRDY pin on SPI comminicaiton
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Forum Post: RE: ADS1256: Electromagnetic interference
Hi Lucas Rosa, You can share your schematic with me privately by requesting a friendship and then sending me a private message. -Bryan
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Forum Post: RE: AFE7222: AFE7222
Hi Drew, Sorry for the delay in communication. So I just used LTSpice for the simulations and I already got back a test PCB. With the above circuit, I am able to scale 0-10V to 0.45-1.45V. I currently have the board wired up in a way such that the AFE7222 operates in half duplex mode. I want to operate it in full duplex mode, such that for testing, I can supply a voltage to the ADC, and the AFE7222 digitizes the input voltage. Since the DAC and ADC portions share the same data bus (wired in 12 bit parallel mode), if I operate in full duplex, the DAC buffers should load in the ADC data, and convert it to an output voltage. I'd like to test it without having to set up an FPGA. Is there a register map I could use to do that? I don't have the dev board, so I wouldn't be able to use the software for the chip. Any guidance here would be appreciated. Thank you, Yousef
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Forum Post: RE: DAC39RFS12: JESD204B/C Protocol for high-speed DAC and ADC converters
Masa, A stream is a stream of digital data. In real modoes a single stream is sent to either DACA or DACB. In complex data modes I accounts for one stream and Q the other. In complex data modes each DAC can output up to 4 I/Q data streams at once via. the channel bonder. Your statement about JMODE1 is correct. If the interpolation is set to 1 (real mode) and a single data stream is being used, only 8 lanes will be used by the DAC. the other 8 lanes will not be used. One could also send 2 real data streams via JMODE1 and use all 16 lanes. This would allow DACA and DACB to have their own streams. Do you know if you plan to use real or complex data and how much data bandwidth you need? Regards, Matt
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Forum Post: DAC63204EVM: Getting Negative Currents from the DAC in a typical setup includign the EVM
Part Number: DAC63204EVM Tool/software: Hi, On the DAC63204EVM Data sheet it references getting negative current from the device. Does this require a negative voltage input to AGND? Or is there some type of configuration that can allow it by powering VDD with 5V and AGND with GND = 0V? If anyone can help with the correct configuration would appreciate it. Additionally, the NVM won't save the configuration after I power the device up again, after being in the GUI. Is there a way to save the setting like automatically keeping hte DAC IOUT running at whatever waveform i set? Because the Program NVM Button on the GUI doesn't seem to work. Thanks! Matt
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Forum Post: RE: ADS1220: Measure of RTD Pt100 with ADS1220 and STM32H7 (over SPI connexion)
Hi Angel, some updates on our side to focus on the pt100 accurate measure. for reference below is our schematic R=pin alone B/W=pin together on the Pt100 3-wire RTD sensor 1.Measure of 1V in differential works fine We are able to measure accurately 1V in differential between AIN0 and AIN1 and the measure were stable over the spi link 2.When plugging the 3-wires pt100 with the following configuration in the driver ADS1220_CONFIG0_PGA_ENABLE | ADS1220_CONFIG0_GAIN_1 | ADS1220_CONFIG0_MUX_AIN0_AIN1 ADS1220_CONFIG1_BCS_OFF | ADS1220_CONFIG1_TS_DISABLED | ADS1220_CONFIG1_CM_SINGLE_SHOT |ADS1220_CONFIG1_MODE_NORMAL | ADS1220_CONFIG1_DR_45_SPS ADS1220_CONFIG2_IDAC_250UA | ADS1220_CONFIG2_PSW_OPEN | ADS1220_CONFIG2_FILTER_NONE | ADS1220_CONFIG2_VREF_EXTERNAL0 ADS1220_CONFIG3_DRDYM_ONLY_DRDY | ADS1220_CONFIG3_I1MUX_AIN2 | ADS1220_CONFIG3_I2MUX_AIN3 I got 0xFExxxx output code instead of 0x2Bxxx (100ohms reference value) Maybe I am missing something in the configuration or in the wiring ? Much regards, Zabieru.
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Forum Post: RE: TPL0102-100: Potentiometer and a timer
Katlynne, Thanks for all your support. I have done the timer using CD4060. Regards Farzaneh
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Forum Post: ADS124S08: PT1000 design requirements and selection of passive parts
Part Number: ADS124S08 Tool/software: Hi Team, Could you please confirm this, as we are using PT1000 instead of the PT100 used in the reference design do we need to replace the passive parts highlighted in the image below? Can this have any calculations?
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Forum Post: ADC34J45: About connection between Analog and Digital ground.
Part Number: ADC34J45 Tool/software: Hello, The ADC34J45 converter only has a pin of ground , which is thermal pad, too. My question is how the connection between digital and analog ground can be performed in this ADC. JESD signal from microprocessor are referred to GND digital but the analog input signals are referred to analog ground, but only a pin of ground is available for this ADC converter. Please, could you indicate us how we should connect the analog and digital ground in this part? Thanks in advance. Best Regards, Pedro
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Forum Post: RE: DAC61402EVM: DAC61402EVM
Hi, Let us know if we could schedule a call this week Thursday or Friday.
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Forum Post: RE: ADC34J45: About connection between Analog and Digital ground.
Pedro, Connect all gnds together. Splitting grounds can lead to unintended inductive ground loops and cause signal quality issues. Regards, Geoff
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Forum Post: RE: ADC12DJ5200RF: JESD pattern maximum length
David, We need more specifics. 1) What is the data rate will the customer will use the SERDES at b/c this will determine how far it can drive/receive? 2) What type of board material is the customer using? 3) Are the traces external (microstrip) or internal (stripeline)? Regards, Geoff
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Forum Post: RE: DAC5675A-SP: Voltage level for driving the CLK pins single-ended
Hi Randall, So the single-ended should have the same swing at the DUT power rail. So if the power rail is 3.3V, the swing should be 0V→3.3V. Regards, Geoff
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Forum Post: RE: ADS1282: Noise Floor is too large
Hi Keith, Thank you for the reply, let me try and I will advise Regards, Iouri
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Forum Post: ADS1278: Figure 88; What is the purpose of the flip flop?
Part Number: ADS1278 Other Parts Discussed in Thread: ADS1274 Tool/software: Hello, On page 38, figure 88 of the ADS1278's datasheet the given schematic is show: I see there is a flip-flop connected to DOUT1 and SCLK of the ADS1274. Is this a D-Flip Flop? What is the purpose of this flip flop? If I wanted to utilize the SPI communication method at a CLK Frequency below 27 MHz is this flip-flop essential? Thank you
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Forum Post: TSW14DL3200EVM: FPGA Base Starter Project
Part Number: TSW14DL3200EVM Tool/software: Are there any FPGA base starter designs for the TSW14DL3200EVM, DAC123200EVM, ADC14DL3200EVM boards. I saw the post mentioning the firmware was developed by a third party, but there must be a general "hello world" starter design with a xdc file at least? This is a standard with most FPGA evm boards in this industry. Thanks, Dennis Bearden
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Forum Post: RE: TSW14DL3200EVM: FPGA Base Starter Project
Hi Dennis, Keep in mind our data capture boards are not meant to be as a development kit. We develop these boards strictly to capture data and parse it over to the PC or laptop in order to display the converter's performance. Typically customers would purchase a Xilinx development kit or similar where you would use Vivado SW tools in order to develop your own FPGA FW. Let me look and see what we might have for you to start with. Give me a few days to get back with you. Regards, Rob
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Forum Post: RE: ADS1292: ADS1292 application circuit review request and related inquiries
Hello Grady, Thank you for your post. Can you tell us who the customer is? Regards, Ryan
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Forum Post: RE: TSW14DL3200EVM: FPGA Base Starter Project
Hi Dennis, We unfortunately don't have a reference design in shareable form. The third party firmware is a closed architecture that is distributed only as a bitfile (to enable the evaluation platform). That said, the core of the capture datapath is the Xilinx HSSIO IP, which can be autogenerated using Vivado's IP wizard. At bitrates higher than 1.25Gbps, the wizard will create an IP configured for native mode, and the XDC is also auto-generated as you can enter the pin/clock connections into the wizard. Regards, Ameet
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Forum Post: RE: AMC1306E05: is there non-isolation device to propose?
Hi Aki, You can take a look at TI's precision ADC portfolio. This link should take you to their product selection page with the delta sigma modulator filter set. Thanks
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