Izik, Was this the app note you are referencing? page 5 seems to touch on this. Oddly I can only find drafts of this application note that were posted on E2E. I'll check in with the team why that is, and see if there might be alternative solutions that could work for you. best regards, -Steve Wilson
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Forum Post: RE: DAC38J84: Level of spurs due to periodic SYSREF
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Forum Post: RE: TLV320AIC3204: ADC Bypass Using Mixer Amplifiers
Hi Diego-san, Thank you for your prompt reply. I understood and will contact you again if I get additional questions from our customer. Best regards, Kato
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Forum Post: RE: DAC3174: DAC3174
Hi Richard Thanks for the suggestion Regards Vikas.
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Forum Post: RE: TLV320AIC3254: Silence detection based on wifi_audio_app with CC3200
Hi marcel_12 I am trying to interface tlv320aic3254 with raspberry pi. Can you please help me ..? How you made connections using CC3200 and raspberry pi , tlv320aic3254 ..? I will be greatful if you help me... Thanks, Shrikant
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Forum Post: RE: DAC8871: settling time from +10V to -10V
Hi Ryuji-san, My apologies for the delay. As I had mentioned earlier, the EVM is mainly designed for DC performance evaluation and hence, it is not a godd idea to test settling time in a similar circuit. In case you have used OPA211 in your circuit, you can replace it with a high-speed opamp like THS4011 in order to get better settling time. Please note that you need to use a high-speed oscilloscope and probes for measuring this parameter. I think THS4011 is pin-2-pin with OPA211 . You can replace and test again. As the DAC is unbuffered, it is better to check the settling time after the opamp. Regards, Uttam
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Forum Post: RE: PCM5102A: can PCM5102 be damaged , if DVDD supply is 0 V (short to GND) ?
As these values do not match the datasheet, I recommend you replace the device. In addition, you should inspect the board to ensure that there is not some other short, like a digital line accidentally shorted to GND or a higher voltage supply. Thanks! Paul
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Forum Post: RE: TLV320AIC3104: I2C
Hi Luis , I had one doubt, What happens I connect MIC2 L/R both to Right ADC . Will I get Audio on Right ADC?
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Forum Post: PGA970: Does PGA970 support 3-wire LVDT sensor
Part Number: PGA970 Dears Does PGA970 support 3-wire LVDT sensor?
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Forum Post: RE: PCM5102A: can PCM5102 be damaged , if DVDD supply is 0 V (short to GND) ?
Thanks Paul, i think the same...i will try and then tell... best regards Alfred
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Forum Post: RE: DAC8775EVM: dac8775
Howdy Siddhant and welcome to the e2e forums! Have you been able to verify the SPI transaction by reviewing an oscilloscope capture? The SPI communication command consists of a write address byte and a data word for a total of 24 bits (when CRC is disable). Additionally, you will need to verify the timing requirements are met, which are shown in the "Timing Requirements: Write and Readback Mode" section of the datasheet -- page 13. Unfortunately we don't have any examples of VHDL code for the SPI transaction, but if you are opting on using a microcontroller platform for communication, such as the MSP430 or similiar, I would recommend that you visit the TI microcontroller forum. They may be able to provide you with assistance in writing the SPI routine using Code Composer or a similar IDE. Best Regards, Matt
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Forum Post: RE: DAC38J84: Level of spurs due to periodic SYSREF
Izik, The Application report I liked to is simply unreleased but the information is all accurate. pg 5: "The distance of the spurs to the main signal is at the SYSREF frequency". best regards, -Steve Wilson
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Forum Post: RE: DAC38J84: Level of spurs due to periodic SYSREF
Hello What would be the spurs level (in dBfs) and does it related to the DAC output freq or to the sysref freq?
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Forum Post: RE: ADS54J60EVM: Inconsistent setup behaviour
Hi Richard, I just looped in our apps engineer, and you should hear back soon. best regards, -Steve Wilson
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Forum Post: RE: TSW1400EVM: Is there other TSW baord can replace TSW1400?
Rocky, I've emailed you regarding the TSW1400EVM shortage, It does appear that there will continue to be a shortage due to very high demand. Unfortunately, I do not believe that there are any other TSW boards that can be used with the AWR1642 . I've sent you a connection request, I can keep you informed of the TSW1400EVM stock status, as updates are available. -Steve Wilson
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Forum Post: RE: ADS54J60EVM: Inconsistent setup behaviour
Cheers, a few moments ago I did have it in a state that looked like it was sync'd at working but haven't managed to recreate it. The standard behaviour seems to be; the sync line from the FPGA is low but the ADC is throwing out what looks like samples on the lanes rather than sync/alignment characters and therefore nothing appears on the rx_tdata bus at the output of the core.
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Forum Post: RE: ADS54J60EVM: Inconsistent setup behaviour
Richard, If you are sending an external 1GHz clock to the LMK, you must use the LMK device in external clock mode. Can you send screen shots of the LMK output clocks and sysref and sync tabs? There are certain settings that must be set and I think you may have one of these wrong. Regards, Jim
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Forum Post: RE: DAC3482: some problems with DAC3482 using the internal 4 fold interpolation
Hi Xingwei, Are you using the DAC3482EVM ? If so, please have a look at the attached power points that will have your DAC exhibiting the proper output (at the desired FDAC rates using the PLL). (Please visit the site to view this file) (Please visit the site to view this file) You will need to load these register files. They include the register settings that you posted. (Please visit the site to view this file) (Please visit the site to view this file) The only thing I needed to modify (for both configurations) was the FPGACLK1 divider in the CDCE. The preset value is 16, and it needs to be changed to 4. Example of this is in the attached power points. Regards, Dan
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Forum Post: RE: ADS54J60EVM: Inconsistent setup behaviour
For the case where I'm using the refClk to drive the core (125MHz). The SYSREF is setup to be 3.125MHz. I have also tried reconfiguring the Xilinx core to use separate ref and glbl clocks. For this I change the clkout 0 divide to 4 to drive refclk with 250MHz and enable clkout8 with a divider of 8 to provide the glbl clock.
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Forum Post: RE: ADS1120: Input Range With PGA Bypassed
Hi Jacob, The answer to you question is yes. The ADS1120 will always measure differentially in the respect of AINP relative to AINN. If AINP is greater in voltage the output code is positive. If AINP is less than AINN the output code is negative. In the single-ended case, you will only see positive output codes as AINP cannot go lower than AINN (AVSS=AGND). Best regards, Bob B
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Forum Post: RE: ADS1232: ADS1232 interfacing with stm32f429
Hi Nikhil, Welcome to the forum! Unfortunately I cannot give you example code for ST devices nor tell you how to connect or communicate with the ADS1232 . You may find that using a bit-bang approach with GPIO is actually easier than using an SPI hardware peripheral due to the odd number of clocks involved for offset calibration and monitoring of DOUT/DRDY for a high to low transition. We do have project code for the MSP430F449 used in the ADS1232REF . It may be a little hard to follow as the code uses freeRTOS. The most helpful code will be in the ADS1232 .c and .h files. ftp://ftp.ti.com/pub/data_acquisition/ADS123xREF/ADS123x_CDROM/Firmware/Firmware_Source_Code/Source_for_123XREF_firmware-1.1.0d.zip Best regards, Bob B
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