The VIH specification applies to all the digital lines on the device (D0-D15, WR, A0, A1, RS, LDAC, and RSTSEL). Let me know if you have any more questions, Thanks! Paul
↧
Forum Post: RE: DAC8822: VIhmin of digital datalines
↧
Forum Post: RE: TINA/Spice/AMC1301: Why the output voltage will have such a huge value when the input voltage is zero ?
Hi James, The AMC1301 model needs updating. We'll let you know when its completed.
↧
↧
Forum Post: RE: ADS54J60: ADS54J60 IBIS
Please use the IBIS Model for the ADS54J40 it is the same. www.ti.com/.../sbam205
↧
Forum Post: RE: PGA411Q1EVM: A few issues
My apologies for the delay. For your first question, the ORS pin or the OEx pins will be active at one time. The XEXT_AMP selects between the two options. They will not both be active at once. Let me know if you need anything else. Thanks, -Clancy
↧
Forum Post: RE: ADS122U04EVM: Error in EVM BOM
Kudos Doug! You found a cut-paste error. For the 0.1uF cap the AVX part number should be 0603YC104JAT2A. Keep in mind that the actual passive components installed on the EVM may not be what is listed in the BOM. The parts may have a substitute installed due to availability of the component listed in the BOM. The key factor is the substitute component must follow the characteristics in the BOM description as to value, voltage and grade (or better grade). There is usually nothing special regarding the components used, but rather common components used in our TI libraries. Best regards, Bob B
↧
↧
Forum Post: RE: PGA411-Q1: The power supply design guide
Nick, For a 120 Ohm load and VEXT = 12V, the VCC + QVCC current is about 135mA. For a robust design, I recommend using at least a 400mA 5V supply for VCC, QVCC, and VIO. Designing for the extra current capability makes the start-up process smoother as well. If you wish to use a smaller 5V supply, then make sure to add resistance between VIO and VCC as mentioned in the "power supply considerations" section of the datasheet. Thanks, -Clancy
↧
Forum Post: RE: ADS122U04EVM: Error in EVM BOM
Hi Bob, I figured it was a copy / paste error, I just happened to see it when I was boiling down the EVM design to a small breakout board. Thanks, Doug
↧
Forum Post: RE: ADS131A02: Noise and internal reference query
Hello Matt, 1. Thanks for the comparison. I have decided to proceed with using the internal charge pump. I am assuming that there is negligible impact to noise contributed by doing so. Can you please confirm? 2. I was going to use it as a reference point in a comparator. I don't need to do that anymore so won't be touching that pin. Thanks, Rohit
↧
Forum Post: RE: ADS7952: review sch of ads7952
Joyce, Please find below our inputs. Let us know if you have questions ADS7952 Schematic Review a) MXO (PIN 7) is called out twice in the schematic. Change second MXO to AINP (PIN 8). TP191 should be connected to AINP (PIN 8). b) Also, consider including an optional RC filter between TP191 and AINP. c) CH6 and CH7 are not used. It’s better to connect unused inputs to GND using a pull-down resistor (10k). d) GPIO pins power-on default is input. It’s better to terminate unused inputs to GND using a pull-down resistor. Note GPIO pins on ADS795x will be useful to turn on/off any switches, enable device or turning on relays especially in case of isolated battery monitoring. e) Could you share more information from where HV_12V and HV_5V and other signals are coming? Note full scale input range is 0 to 2Vref=5V (if range 2 is selected and VA = 5V). It might be good to consider input clamp protection on ADC input channels like CH4/CH5 if expecting any transients on those high voltage lines that can couple to input of the ADC. f) According to ADS795x Data Sheet, REFP pin requires a 10uF ceramic capacitor to meet performance. Please increase C43 to 10uF. g) ADS7952 _CS line should be connected to the MCU. There’s no need to use a pull up resistor (R130). Thanks, Vishy
↧
↧
Forum Post: RE: ADS1293EVM: ADS1293EV IEC compliance test, input impedance
Hello Ted, I'm trying to replicate the test on the bench with the ADS1293EVM as well. One detail that I still want to clarify with you is the input voltage amplitude. Where does the standard specify the amplitude, at the source or P4? Keep in mind that the source voltage is divided down by 1/1000 before P4. My assumption is that the input source should be 1Vp, and P4 will be 1mVp. Then, you should see 1mV at the output as well, with or without the +/-300mV offset. I was able to verify this on the EVM using the standard 3-lead ECG settings. Best Regards,
↧
Forum Post: RE: ADS7952: review sch of ads7952
One more comment: TLX9291A is a photo coupler. What's the correct amplifier part number customer plans to use? Thanks, Vishy
↧
Forum Post: RE: ADS1210: About resolution
Hi Ohno-san, Unfortunately I cannot read the OCR or FCR data from my test setup, so I don't know what to expect or if the FCR changes much over data rate. Offset calibration is done first and is removed from the result. Then the reference is applied and a conversion factor is determined to use a multiplier on the ADC result (minus the OCR value). If there is an issue with gain calibration, this may be a result of noise or instability of the reference. Lower data rates could average the result reducing the noise. The Calibration section on page 13 of the ADS1210 datasheet discusses taking repeated calibrations at higher data rates and averaging the FCR and OCR results and writing the contents back into the registers. This allows for adjustments as required so you are not strictly bound to the self or system calibrations. I still have concerns regarding the discussion from: https://e2e.ti.com/support/data_converters/precision_data_converters/f/73/p/616715/2273734#2273734 If a system calibration is used, then it is quite possible to see gain error as was discussed in the thread. For me to give more specific reasons or explanations, I would need to know more specific information on how the calibration is being done and whether the calibration is self or system calibration. Best regards, Bob B
↧
Forum Post: RE: ADS7952: review sch of ads7952
Another comment: Decoupling capacitor value on the supply lines is not very clear. Data sheet recommends a 1uF ceramic capacitor at each supply pin and must be placed as close as possible to the device. Thanks, Vishy
↧
↧
Forum Post: RE: TLV1578: TLV1578 alternatives
KF, TLV1578 is a 10-bit ADC with parallel interface. Is parallel interface ok? I guess you meant TLV1548 . This is a 10-bt SAR ADC with serial interface but wake up to conversion result is longer than a few us. I would suggest customer look at first www.ti.com/.../ads7955 It has very low leakage current and 1us wake up time. Thanks, Vishy
↧
Forum Post: RE: DAC3482: some problems with DAC3482 using the internal 4 fold interpolation
Xingwei, We are looking into this. Regards, Jim
↧
Forum Post: RE: ADC12J4000EVM: Is the JESD transmitter in ADC12J400 keep sending data continuously?
Hi Jim, Thank you very much. I checked the Link Error Status of the JESD receiver in FPGA by reading the register space. I found that some link errors, such as unexpected K-character, disparity error and not in table error, occurred occasionally. The errors occur can occur in any JESD lane. I checked the link parameters (such as LMF, K) and verified that the FPGA and ADC share the same configuration. I don't know what else I can do to solve this problem. Could you give me some suggestions of how to fix them? Regards, Tong
↧
Forum Post: RE: ADC12J4000EVM: Is the JESD transmitter in ADC12J400 keep sending data continuously?
Hi Tong Here are a few different things to try: If you are using the default EVM configuration settings, the clocks sent to the FPGA capture board will not be optimized for the Xilinx JESD204B IP. In that case it will be necessary to change the LMK04828 clock dividers slightly to meet the Xilinx requirements. The TSW14J10EVM User Guide includes the required clock frequencies for the Xilinx IP. http://www.ti.com/lit/pdf/slau580 Please refer to Sections 6, 6.3 and 6.4 for details on configuring the ADC12J4000EVM for Xilinx use. You could try using a slower ADC clock frequency. If the link errors go away the issues may be due to signal integrity problems at the higher clock rate. If that is the case, changing the ADC12J4000 JESD204B transmitter pre-emphasis settings to a higher or lower value may improve performance at the higher clock rate. Let me know if either of these approaches help. Best regards, Jim B
↧
↧
Forum Post: RE: DAC8871: settling time from +10V to -10V
Hello Uttam san, Sorry for bothering you but I'm looking forward to your reply. Best Regards, Ryuji
↧
Forum Post: RE: TINA/Spice/AMC1301: Why the output voltage will have such a huge value when the input voltage is zero ?
Hi Tom, Thank you for your help, and please keep in touch when the module is updated. Best regards, James
↧
Forum Post: RE: ADS8688EVM-PDK: Some problem on the ADS868X EVM GUI
This has been communicated by offline.Thanks.
↧