Forum Post: RE: ADC12QJ800: Bypass SYSREF windowing for low CLK freqs
Hello David, Yes if your sysref can meet setup and hold for the ADC without calibration then it is not required and can be ignored. You can easily check if you are meeting setup and hold on the ADC...
View ArticleForum Post: RE: ADS5271: Reference differential voltage
Hi Julien, Thanks for the update. A few more questions. In your design are you DC coupled to the analog inputs of the ADC on any or all the channels with an amplifier? How stable are the power...
View ArticleForum Post: RE: ADC34J23EVM: Unable to configure ADC & LMK04828 using ADC3000...
Hi Rob, I intend to use the on-board LMK04828 to generate the ADC sampling clock (LMK DCLKOUT0), FPGA GBT reference clock (DCLKOUT2) & the FPGA JESD core clock (DCLKOUT8), and have set the jumpers...
View ArticleForum Post: RE: ADC34J23EVM: Unable to configure ADC & LMK04828 using ADC3000...
Hi Sukhdeep, Thank you for the details. Can you please probe the clock inputs with an oscope to make sure you are getting the sampling frequency that you expect? Thanks, Rob
View ArticleForum Post: RE: ADC34J23EVM: Unable to configure ADC & LMK04828 using ADC3000...
Hi Rob, I have probed the LMK clock outputs, and I do not get the desired sampling frequency, which is the issue: no matter how the chips are configured in the ADC3000 GUI, the settings do not take...
View ArticleForum Post: RE: TSC2200: Failed to read VBAT, VBAT 2, AUX1 and AUX 2 voltage...
Hi Kevin, I took a look and your schematic looks fine, but your code did not seem to include where you were setting the registers, just your functions defined. If you can send your code that attempts...
View ArticleForum Post: RE: ADC34J23EVM: Unable to configure ADC & LMK04828 using ADC3000...
OK thank you for confirming. Might be good to troubleshoot thru the schematics. Is the 100MHz oscillator on board and powered up? If so, is there a clock signal on the LMK at pin 44? Also, so make...
View ArticleForum Post: RE: ADS1258-EP: Using DMA with ADS1258
Hi Greg Baghdikian, Thanks for clarifying, this might be possible. Basically you can toggle the START pin and keep it high so the ADC continues looping through the sequencer wait for DRDY to drop low...
View ArticleForum Post: RE: ADS1248: ADS1248 Radiation Report and Reliability Data
Hi Mehmet YILMAZ, The ADS1248 is a catalog commercial grade device. Therefore there is no radiation report to share -Bryan
View ArticleForum Post: ADS9218: Common Mode Rejection Ratio
Part Number: ADS9218 Tool/software: Hello, For the ADS9218, I see that the electrical specifications call out that the common mode voltage of the analog inputs must be within Vocm +/- 0.05 mV, and...
View ArticleForum Post: RE: ADS7067: Guaranteed max Reset time to not destroy the component
Hello Michael, I apologize for the confusion and I will clarify, for an occasional situation of resetting the device by switching off the AVDD within a very short time span and without removing an the...
View ArticleForum Post: RE: ADS1299: ADS1299 - 2 ICs Settings (SRB, BIAS)
Hello Rajasree, Thank you for your post. The same AVDD and AVSS supply voltages can be shared between the two ICs, the supply source is capable of providing the necessary current. The sharing of...
View ArticleForum Post: RE: DAC8775: DAC Voltage output frequency response
Hi Veselin, Apologies for the delay, I am checking if we have any available test data for the frequency response. I will get back to you once I can find this data. Thank you, Lucas
View ArticleForum Post: RE: ADC12QJ800: Bypass SYSREF windowing for low CLK freqs
What are the setup and hold times when calibration is ignored?
View ArticleForum Post: ADC12QJ800: sampling clock delay going through PLL
Part Number: ADC12QJ800 Tool/software: We have two ADCs receiving delay matched device clocks, then PLLs used to derive sampling clocks. Is there delay, or more importantly, temperature dependent,...
View ArticleForum Post: RE: ADS7044: Input load / design review
Hi WorkerBee, Sorry I couldn't get to you last week. You've done a great job of digging into this yourself, but let me cover a few points you made. I should clarify the benefits of oversampling....
View ArticleForum Post: RE: ADS7128: How to correctly use RMS
Hi Daniel, Sorry for not getting back to this sooner. That's interesting behavior I haven't seen before. Can you confirm what supply voltage you're giving the device, and what decoupling capacitor...
View ArticleForum Post: RE: ADS7952: ADS7952 channel slection
Hi Chandra, It does seem like the phase which you are changing SDI on the controller is wrong. The controller should change data on the falling edge of SCLK, so that it is stable by the rising edge of...
View ArticleForum Post: RE: ADS7057: Conversion Time and Falling Edges
Thanks JM. I don't recommend only 16 falling SCLK edges simply since the datasheet explicitly requires 18. Especially if you can afford the time it takes to use 24 SCLK falling edges without impacting...
View ArticleForum Post: RE: ADS1298ECGFE-PDK: Support software for Win10/11
Hi, How about the situation going? Will you give me your advice? Regards, Takumi
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