Hi Greg Baghdikian, Thanks for clarifying, this might be possible. Basically you can toggle the START pin and keep it high so the ADC continues looping through the sequencer wait for DRDY to drop low the first time send the RDATA command, and ensure the STATUS byte is enabled. This requires 40 SCLKs (8-bit for RDATA, 8-bit for STATUS, and 24-bit for ADC data) Continue sending this same frame (40-bits) until you get all data from however many channels are enabled in the sequencer Ensure that you are clocking out multiple complete 24-bit values between DRDY toggling, as some of them will be corrupted or not new data. I would suggest setting the SCLK speed so you clock out at least two complete frames in each conversion period Use the DRDY bit in the STATUS byte to determine which data is new, and used the CHID bits to determine which channel you are measuring in that frame I tried this on the EVM, see below. I am only showing two frames worth of data, but I had all 16 single-ended channels enabled and I was operating at 23.7kSPS. Let me know if you have any questions about this information In parallel, I will have one of colleagues reach out to you for more info on a new part that might fit your needs -Bryan
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