Forum Post: TLA2528: TLA2528
Part Number: TLA2528 Tool/software: Hello, I am going crazy when trying to read adc values from TLA2528. The I2C single register read and write is fine. I set the FIX_PAT_ENABLE flag on register...
View ArticleForum Post: RE: ADC12DJ5200RFEVM: JESD204B Mode 61, A & B link FMC routing
Hello Jeff, Unfortunately there is no way to map the B channel lanes to the an A channel output. There are registers to power down the separate channels of A and B which will also shut down the JESD...
View ArticleForum Post: TI-JESD204-IP: TI JESD204C IP simulation issue
Part Number: TI-JESD204-IP Tool/software: Hello, I'm trying to run a simulation in Vivado with the TI JESD204C IP TX and RX cores back-to-back and am seeing that the rx_all_lanes_locked signal out of...
View ArticleForum Post: RE: ADS54J40: Inquiry on how to calculate overall latency of...
Hi JH, Can you provide some additional details on the customer's configuration? The TX delay is dependent on a few factors including Sampling Rate, Interface Rate, and JESD Lane rate. Once we have...
View ArticleForum Post: TX7332EVM: GUI operating system compatibility
Part Number: TX7332EVM Other Parts Discussed in Thread: TX7332 Tool/software: I have followed the steps to install the TX7332 EVM GUI on a machine running Windows 11. However, when it reaches the...
View ArticleForum Post: RE: ADS1298: isolation protection circuit
Hi Avvaru, Thanks for clarifying. Generally such protection circuitry consists of transient voltage suppression (TVS) diodes and high-power current-limiting resistors. For legal reasons, we cannot...
View ArticleForum Post: RE: ADS131M04: N-pin voltage refers to communication issues
Hi wei, It seems you uploaded some images, but failed. Please upload them again. I hope these are timing plots which will be helpful to address your register reading issue. BR, Dale
View ArticleForum Post: RE: ADS1298: Simulation of ADS1298
Hello Varun, Thank you for your interest in our ADS1298. Unfortunately, we do not offer a PSpice or TINA-TI model for our ADS1298 since it is a complex device with an input PGA, RLD feedback...
View ArticleForum Post: RE: ADS1220EVM: Can't Manually install the ADS1220EVM plugin in...
Hi Timo Zellmer , This appears to be a Windows file-permissions error that is preventing the installer from copying files from one location to another. However, this is not a critical step as these...
View ArticleForum Post: RE: DAC82001: Output noise (0.1 - 10Hz) graph
Hi Sato-san, This delay is from an internal T/H deglitcher on the device. The delay is created from a RC time constant, ideally 200 ns. Typically, it would have 10% accuracy or +/-20 ns. The maximum...
View ArticleForum Post: RE: ADS8686S: Bandwidth using Oversampling
Hi Cornelius, The speed of data stream to the digital filter inside the ADS8686S ADC is always 1Msps (sampling rate) whether the internal multiplexer is switching or not, so your sampling rate should...
View ArticleForum Post: ADS1256: Electromagnetic interference
Part Number: ADS1256 Tool/software: Hi Team, I have developed a board with the ADC mentioned. The ADC is about 8 cm from another board (same reference) in which a 5nF capacitor is discharged through a...
View ArticleForum Post: RE: ADC12DJ5200RF: JESD204C AND SERIALIZER LATENCY from...
Hello Ziquan, I am a little bit confused what you are trying to accomplish can you please clarify your question a bit. The deterministic latency is of a JESD system is found by finding your worst case...
View ArticleForum Post: RE: ADC12DJ5200RFEVM: Diagrams in ADCxxDJxx00RF Evaluation Module...
Hello Makoto, Q1. Yes this is correct. Q2. They are not enabled by default as it is not a requirement because all clocks are derived from a single source in both cases actually and do not have to be...
View ArticleForum Post: RE: ADC12DJ5200RF: JESD204 LINK from ADC12DJ5200RF Datasheet
Hello Makoto, Q1. Yes each link transmits data in sync. Q2. If you are not using these lanes you can leave them disconnected. best, Eric
View ArticleForum Post: RE: ADC12DJ5200RF: Device clock calculation
Hello Makoto, For operation of the ADC in JMODE 0 the effective sampling rate of the converter is double what you apply at the input as this is an interleaved mode of operation. So in your case you if...
View ArticleForum Post: RE: ADC34J24: CDCLVP1204 interface ADC34J24 SYNC
hi Rob, I ended up using a biased three resistor voltage divider to set the proper terminating voltage and common mode voltage to the ADC34J24.
View ArticleForum Post: RE: DAC12DL3200: Biasing the outputs
Hi Charan, Its not that straight forward to recommend a specific value. Since you will be DC coupling and using the LMH amp for the level shift you will need to simulate a value that will work first....
View ArticleForum Post: RE: DAC53608: Design Tool for Output Voltage Adjustment using a...
Happy Friday Katlynne, Thanks for your explanation, I think it makes sense though it's not very obvious. Have a good long weekend! Ed
View ArticleForum Post: RE: ADS1256: Electromagnetic interference
Hi Lucas Rosa, Some questions for you: Can you help us understand how you determined the ADC is causing this issue? It sounds like the discharge is causing this issue, which is negatively affecting...
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