Hello Jeff, Unfortunately there is no way to map the B channel lanes to the an A channel output. There are registers to power down the separate channels of A and B which will also shut down the JESD subsystem for that channel. These are default turned off and in this particular mode (61) I would not recommend doing this as it is an interleaved mode. One important note is that on the ADC12DJ5200RF EVM all of the B channel JESD lanes are inverted going to the FMC which is something you will have to account for in your FPGA FW. Additionally, if you would like we do offer custom JESD reference designs to enable fast prototyping on the FPGA side. These designs will be custom for the ADC and mode of operation you choose. If this is something you would be interested in please let me know. Best, Eric Kleckner
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