Forum Post: LM97600 design approach of connecting to FPGA Virtex6
Hello, My customer are reviewing LM97600. And they use Virtex6 as FPGA.Could you please kindly let me know if there are words of caution for connecting ?And if there is application note of design...
View ArticleForum Post: RE: what is the sequence for powering down/up the AIC33
Thank you very much , this has helped us A LOT ,but , it seems that the problem ocuurs less but is still there .We did not manage to do a proper sequence that will leave the "Alll programmed...
View ArticleForum Post: TLV320AIC3204 ADC Processing Blocks
Hi,On my target board BCLK is used as input to PLL.Trying to use ADC Processing Blocks to filter some DC noise.PLL initialization code:I2Cwrite(CODEC_ADDR,0x00,0x00); //Initialize to Page...
View ArticleForum Post: AC lead off in ADS1298
Hi,I have been reading through all the posts here regarding the lead off, both DC and AC in ADS1298 without finding sufficient help. I have managed to get DC lead off to work but not the AC lead off...
View ArticleForum Post: RE: ADS42JB69EVM plus JESD204B Translation Card
Kann,The system requires you to use the TSW1400 to capture the data from the JESD204B translation card. Your other option is to connect a logic analyzer to connector J2, which has the LVDS data and...
View ArticleForum Post: RE: Can I change TVP5150 default horizontal clock divider?
Scott,Sorry but the clocks per line is fixed.BR,Steve
View ArticleForum Post: RE: TLV320AIC34 and TLV320AIC3105 queries
Hi Elvin,No, this is not a good connection. Even for single mic, this is not the way to do it. Mic Det is looking for a DC voltage. Please review Fig 36 and 37 in the datasheet. What these figures...
View ArticleForum Post: RE: High speed differential line receivers
Hi,If you want to ask questions about the different types of LVDS to single ended line drivers, you would need to ask that in the proper forum. This is the high speed data converter forum. But...
View ArticleForum Post: RE: PCM1795 / Limitation of SCK at external digital filter...
Hi Xie-san,Nice to see you and thank you for your response.I confirmed again that they are using PCM mode with external digital filter. I apologize for the confusion.Please let me state again their...
View ArticleForum Post: Delay from CONVERT to ADC sample for AMC7823
Hello,I have two questions listed below:In reviewing the data sheed for the AMC7823 (Revision March 2012) I was not able to determine the relationship between the assertion of the external CONVERT...
View ArticleForum Post: RE: ADS1248: Ambient Temperature Monitor
Aha!Thank you very much, especially for such a quick reply.. I wasn't quite grasping it, but I do now.Muchas GraciasMitchellps Sorry moderator; didn't mean to post in the wrong forum on my first post
View ArticleForum Post: RE: DAC7821 Positive Voltage Supply
Junheng,I meant the ADS1605EVM User's Guide. It's here.
View ArticleForum Post: RE: TAS1020B Sample Rate and MCLK
Praveen,All of my 'recording' TAS-1020B experience has been at 44.1kHz or 48kHz, but I know of no reason the TAS1020B would not support 32kHz. The divisor of 6 should be OK (but is, again, outside my...
View ArticleForum Post: PCM2906 - 0Hz
Hello! Is it possible to change PCM2906 input frequency range down to 0 Hz, to acquire DC voltage directly? I tried to bypass input capacitors, but chip automatically settle to it`s virtual ground...
View ArticleForum Post: RE: ADS42LB69 bit order in QDR mode
Hi Peter,Still waiting on verification, however I think you're right about the bitslip. Have you tried inverting the frame clock? This is the only way I can see that you would get 4,0,12,8.Note that...
View ArticleForum Post: RE: TSW1400
Hi Matt, I tried running the tsw1400 and TSW3085EVM following slau374.pdf user guide ( section 3.5 )Configured the DAC using the file DAC3482_1228p8MHz_2xInt_NCO_30MHz_single_sync_source_mode.txt as in...
View ArticleForum Post: RE: PCM1795 / Limitation of SCK at external digital filter...
Hi Sonoki-san: When you bypass the internal filter, it will also bypass some function. When PCM1795 uses external filter, the max clock will refer to DSD mode. Could...
View ArticleForum Post: RE: Can I change TVP5150 default horizontal clock divider?
Do you have "correct" NTSC, PAL or SECAM into the device? Is the input terminated, AC coupled and filtered properly? Could the problem be downstream of the Decoder? Also, there are many register...
View ArticleForum Post: RE: LM97600 design approach of connecting to FPGA Virtex6
Hi RyujiThe Virtex 6 should work just fine as long as it has the necessary number of GTX transceivers (10) available to receive the LM97600 data. The FPGA will need a reference clock that is...
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