You are correct, I noticed the same thing myself this morning, somehow our logic analyzer channels got changed. This should be fixed now in the following diagram. In the same order the channels are positioned in the diagram: Channel 1 Blue is SCLK, Channel 3 Yellow is SDI MOSI (Master SPI Bus out Slave 1261 In). Channel 0 Purple is DOUT/DRDY (MISO), Channel 2 Green is NOT-CS, I have the Xilinx SPI bus master set to clock quiescent low, clock not active outside word. In this run I ran the bus in manual mode. In this run I also cycle through all three slaves on the bus sending the reset command to the 1261 using a different slave in an effort to see if I could get chip select to move but nCS is not moving at all. Our HW engineer insists CS is hooked up correctly but it is behaving like the Xilinx SPI bus is not driving it regardless of the register setting for the selected slave. Also as you can see the SPI bus is only driving the clock during transmit which means there is no clock available to the 1261 to respond for the second byte. I'm not sure how to fix this. Also, as you suggested, we hooked up a scope to the dedicated 1261 DRDY pin and only set the START pin and did nothing else and there is no periodic signal on the 1261 dedicated DRDY. I think the first priority is to figure out why the 1261 is not responding to START with DRDY and why the Xilinx SPI bus is not moving CS, though I'm not sure yet how to proceed. Below is the latest plot with the channels set up correctly.
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