Hi Sachin Thanks for the input, we changed the source signal. Now we are generating the input signal from FPGA itself from same device clock and now we are not getting this this. But, we are getting an another issue that when we measure the determinstic latency for the setup it remains almost constant but once in 5-6 power cycle we see a drift of 8ns. We are operating at 125MHz device clock, we changed the delay between the device clock and sysref from LMK but still we are getting this issue. Can you help us to debug this issue. I am attaching the scope waveform in both the cases for your reference. with 8ns variation without 8ns variation
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