Hi Richard,
For Xilinx STA, we have to mention a OFFSET IN for the input constraints. It basically tells what time before the clock edge the data is ready, and valid through how much time!
Accordingly, from ADS54RF63 datasheet, my understanding is that my data could worst case come 0.25 ns after clock egde, and will be valid until ( Period/2 - 0.25 ns) .i.e 10.4165 - 0.25 = 10.167 ns!
Thus, I would write : " TIMEGRP "data_in" OFFSET = IN -0.25 ns VALID 10.167 ns BEFORE "dry_clk_inp" RISING; :
Could you please tell me if this is right or wrong?
I also have doubts that I am getting noisy data because of setup time, hold time violations! Please comment.
Thanks a lot,
Basil.