Wow, thanks for the quick response Tom! Yes, average I_digital & I_analog. I will use the total current at shutdown for a y-intercept of a current formula: I_total = I_shutdown_total + (F_oper / F_AppNote) * I_normal_total. I can also use I=CVf to adjust I_digital for 3.3V operation as opposed to the datasheet's 5V.
I still need to know the split (or ratio) between I_digital & I_analog so I can bias my Vref creating V_digital. It's hard for me to measure & my sample size would be small. Total is 3.1mA max. Is that 1mA analog & 2.1mA digital? 3mA analog & 0.1mA digital?
I always try to 'leverage' the app circuit example, but here the FPGA interface was not 5V-tolerant in all cases. Using a zener near it's knee for ~3.5V seems like the best low-power way to protect the FPGA. Not a low R_out 3.3V supply, but also not wasting 150mW to power a 1mW part. A simple voltage divider fails if I_digital ever goes too low. In my previous design using this ADC, increasing resistance of the isolation resistor from 51 Ohms & adding 'local battery' of bulk caps on V_digital worked fine.
Thanks again for quick info, & I look forward to those average currents!
Paul
