Hi, The TSW1400 capture card uses an Altera FPGA to capture data from the ADS5463 EVM as well as many others, and the Altera Quartus project files are available for download from the TSW1400 page at http://www.ti.com/tool/TSW1400EVM?keyMatch=tsw1400&tisearch=Search-EN-Everything under the Software section. Our firmware source code is in Verilog, however. Not VHDL. Also, there is a TI Design available http://www.ti.com/tool/TIDA-00069 that covers how to implement a typical LVDS interface to our ADCs and DACs using the ADS4249 as the ADC rather than the ADS5463 , but the source code could be adapted to the LVDS formats used by other ADCs. Regards, Richard P.
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Forum Post: RE: ADS5463EVM: VHDL code
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Forum Post: RE: TLV320ADC3101: TLV320ADC3101 I2S Buffer/I2S Clock Settings
Hi Luis, Here is the header file I am using. I tested writing a value and reading it back on I2C and it seemed to work. I just changed a few things in the header file: the PLL values, as stated before, and the input for each ADC (I tried putting all inputs in case we missed our mic). Thank you so much for you help. All the best, Nicole (Please visit the site to view this file)
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Forum Post: RE: PCM5242: PCM5242 Suggested Diff to SE buffer
The datasheets for the OPA1688 and OPA1622 both show differential to single-ended conversion on a DAC output in the applications section. If you are only planning for 600 ohm headphones, and none of the lower impedance types which are a much more difficult load for the amplifier, then I would suggest the OPA1688 . http://www.ti.com/lit/ds/symlink/opa1688.pdf Differential to single-ended conversion using a difference amplifier with equal resistance values results in a gain of 6 dB. The DAC noise is a differential input to the circuit, so the DAC noise will be amplified by 6 dB as you found. Only DAC noise which is a common-mode (equal in magnitude and phase at the DAC outputs) would be removed by the difference amplifier. Best regards, Ravi
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Forum Post: RE: ADS1255: PGA settings
Hi Ziga, The command to change the PGA gain should be very similar to the commands used to initialize the device. However, instead of writing to multiple registers you can just write to the ADCON register if all you need to do is change the PGA gain. The command sequence for this would look like: 0x52, 0x00, . Just make sure that the device is in SDATAC mode before attempting to write to the device registers. You may need to send the 0x0F command before the WREG command sequence shown above. After changing the PGA gain, you'll probably need to restart the ADC conversions. You can do this by sending the SYNC (0xFC) and WAKEUP (0x00) commands (as shown in Figure 19 of the datasheet). This makes sure that the next result is settled and correctly represents the new value with the updated PGA gain. By chance, do you enable auto-calibration during initialization? If so, then keep in mind that changing the PGA gain will trigger a calibration and you'll need to wait for the calibration to complete (/DRDY will go low) before doing anything else. Best Regards, Chris
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Forum Post: ADS1256: Cannot change data rate with WREG 53h command
Part Number: ADS1256 Hello TI Forum, I am trying to set the data rate to something other than the default 30kHz. My XTAL1-CLKIN is 7.68MHz. I try to send 53h, 00h, 03h which should change the data rate of the /DRDY line to 2.5SPS. But this is not happening. I also cannot set the DIO lines to output high. I can do a data read and get a correct input voltage reading across AIN_0 to AIN_7. The timing of the SPI looks correct to me. I've attached o'scope shots. It seems I can clk data out of the part, but the part does not WREG commands. Thanks for any help, Robert B
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Forum Post: RE: ADS1220 SPI mode settings
Hi Dan, We know that if the DVDD supply ramps too quickly there can be an issue with the ADS1220 not coming out of the power on reset. The result is DOUT/DRDY are always high, and no communication with the device is possible. Please see the latest ADS1220 datasheet on page 60 and section 10.2. Monitor your DVDD supply at the ADS1220 input and make sure that the supply ramps at the proper rate. Best regards, Bob B
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Forum Post: RE: PCM5242: PCM5242 Suggested Diff to SE buffer
Thanks for the feedback Ravi. Is there a part similar to the 5242 with higher SNR or is the 5242 best in its class?
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Forum Post: RE: DAC38RF83: DAC does not output and unable to change the Page Select Register.
Seth, Is this on a custom board or a TI DAC EVM? Are you using our GUI? Can you send me the parameters you are trying to run this DAC (sample clk, LMFS mode, sysref, PLL or ext clk mode, ect...)? What FPGA are you interfacing to? If you have a complete DAC configuration file you can send, we will look at that as well. Regards, Jim
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Forum Post: RE: Input Driving circuit for ADS4249
Hi Prashanth, In-addition to what Jim suggested, you could use the below circuit using LMH6554 (fully differential amplifier) for driving the ADS4249 in DC-coupled mode. The below circuit configures the LMH6554 for a gain of 1. You may have to redo the output low pass filter depending upon the input and output impedance of the filter you select. The LMH6554 is optimized to drive a 200-ohm differential load. So, the selection of Ro and ADC termination resistors that gives overall 200-ohm differential load at the LMH6554 output while designing the low pass filter would be ideal. Best Regards, Rohit
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Forum Post: RE: ADS1278: Differential Input Signal Interface Polarity (Figure 89 on the datasheet)
Hi Cagatay, Thanks for your post. The designators "AINP" and "AINN" correspond to the ADS1278 inputs, not the amplifier outputs. You are correct that the polarity of the amplifier output pins is reversed from the polarity of the input pins; however, the output pins of the amplifier can be connected to either input of the ADC, depending on routing constraints or application criteria. Sorry for the confusion. Best Regards,
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Forum Post: RE: PCM1861EVM: PCM1861EVM Samples
Hi, Ranjith, Yes, any EVM of the PCM186x family of Audio ADCs will include a USB-I2X board. Best Regards, -Diego Meléndez López Audio Applications Engineer
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Forum Post: RE: ADS1243: ADS1243 - how to read all channels in continuous mode?
Ondrej, I'm sorry if I wasn't clear. Sending the DSYNC command will require an extra write to the device to start the conversion since the actual conversion is started on the next rising edge of the SCLK. So what you would need to do would be send 1. Set the multiplexer to the proper input 2. Send a DSYNC command to restart the digital filter and start a conversion 3. Send a command to initiate the conversion (see below) 4 Wait for a /DRDY to indicate that the conversion has completed 5. Read the data 6. Set the MUX to the new input and repeat the sequence For step 3 (send a command to initiate the conversion), I suspect that you could issue a dummy command such as writing 00h to the device, which would be the same as an incomplete read operation. This should start the conversion. You mentioned that you used a RREG command after the DSYNC and the conversion was not started. Normally, I would have expected that to work and I'm sure I've seen others use that to start the conversion for a DSYNC. I'm not sure what is wrong with your setup for that. Can you grab an oscilloscope shot of that transaction? It might be best to use an logic analyzer so that we can read the bit transactions. As for the comment on page 10 about minimizing the error and synchronizing the MUX change, this was meant to address what happens when you change channels, but do not run a DSYNC command. Here is an example: the device is in the middle of a conversion and you change the channel in the middle of the conversion without the DSYNC command. The conversion that comes out will be a combination of the measurement of the two channels. With this type of ADC, the output is similar to a running average (or really a weighted average) of the input during the conversion period. If you could synchronize the MUX change so that it occurs right after the DRDY, then there is a minimal amount of time that the ADC looks at the previous channel for the next read. Often, the data periods are long for the ADS1243 . If you're running at 7.5SPS, then the data period is 133ms. If you are able to change the channel within 20us of the /DRDY, then the error that you will see from looking at the previous channel will be moderately small. If you use the DSYNC you don't have to worry about this. If you change the channel and then run the DSYNC, you restart the conversion. During that data period, the ADC would only see one channel. I would also note that many of our newer devices are easier to use. When the MUX changes in devices like the ADS1220 , ADS1248 , and ADS124S0x, the conversion restarts automatically, without the need for the DSYNC command. However, if you do need to make synchronize a conversion for other reasons, you are still able to do so. Joseph Wu
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Forum Post: DAC8832EVM: DXP issues with DAC8832EVM
Part Number: DAC8832EVM Hello, I am trying to use the DAC8832 EVM but after setting up the DXP software and trying to generate a waveform with all the defaults in place, I don't really see the output that I was expecting. I was trying to generate a square wave with a frequency of 35Hz. Here is how I have my DXP set up while trying to generate my square wave. As I stated before I have all the default configurations for the EVM in place and I am reading the generated signal from the designated pin (J1-2). I also had issues with downloading the .XML file for my EVM and I used the file provided by a previous E2E post . So this may be an issue? I tried changing some of the options available to me, such as the source, offset voltage, and frequency but it still did not look much better. Thanks, -Oscar
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Forum Post: RE: TLV320ADC3101: TLV320ADC3101 I2S Buffer/I2S Clock Settings
same problem here!!
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Forum Post: RE: ADC16DV160 - DC Offset Issue on Captured Data
Hi Sarika There is nothing in the ADC structure or output timing that will result in different results between the first 2k and later samples. I recommend reviewing your data capture and storage design to identify the cause of the error bits when the sample depth is increased. Best regards, Jim B
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Forum Post: RE: ADS1256: Cannot change data rate with WREG 53h command
Hi Robert, Welcome to the TI E2E Forums! Your command sequence looks okay (and the scope shots would indicate that you're operating in the correct SPI mode: clocking data in during the SCLK falling edge). I would suggest sending the SDATAC command (0x0F) before any WREG commands to make sure the device is in SDATAC mode. In RDATAC mode, you may not be able to write to the device registers. ...I think that ought to clear up the issue. If not, then I might start to question the signal integrity since there appears to a bit of ringing on all of the SPI signals with each SCLK transition. You might consider adding a 50 Ohm series resistor on the SCLK signal to slow down the clock edge rate and help reduce the capacitive coupling of SCLK into the other SPI signals (as well as help with the ringing on SCLK). Keep in mind that the scope probe adds some parasitic capacitance to each of the signals and helps slow down the clock edge rates; therefore, when the scope probe is removed the signal integrity may actually be a bit worse than what is shown. Best Regards, Chris
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Forum Post: RE: Can ADS54J66EVM interface with ZC706 Dev-board correctly?
Really thank you Jim. I got the reason!!! Because our power supply have the 1A current limitation. When I load the LMK configuration file, the current is 0.93A. After the ADC configuration file is loaded, the current change to 1.28A. In your user guide ADS54J/58J6x Evaluation Module User's Guide (Rev. D) , the power supply with a minimum current source of 3 Amps is required. I really sorry for trouble you about my stupid mistake. Sincere thanks for your kind help.
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Forum Post: RE: Can ADS54J66EVM interface with ZC706 Dev-board correctly?
Yuzhen, You are not the first customer to have this problem! Glad you are up and running. Regards, Jim
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Forum Post: RE: ADS1262: Unable to capturing serial data coming DOUT/DRDY pin
Hi Shambhu, [quote user="shambhu hosamani"]OPCODE 1 = 45h, OPCODE 2 =00h,REG DATA1= 5Dh,REG DATA2=00h,I have selected following[/quote] In this case, you're only writing to a single register; therefore, you do not need to clock in the "REG DATA2" byte. You only need to provide a single data byte here! After you send the above WREG command, have you tried using the RREG to read back the register configuration for verification? Best Regards, Chris
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Forum Post: RE: ADS5463 Minimum Sample Rate
Hi, Sometimes an ADC might have phase locked loops to lock on to the clock and in that case the PLL might impose a lower limit on the clock frequency. Other ADCs that have an LVDS DDR output may have a duty cycle correction circuit to make the input clock become 50/50 duty cycle for the output DDR clock even if the input clock is not 50/50 duty cycle, and that type of circuit also imposes a lower guaranteed sample rate. The ADS4149 device you were using has such a duty cycle correction circuit which is why the datasheet listed 20Msps as the lower guaranteed limit. You may find the device to operate at a lower sample rate, but the risk would be that another device from a different production lot would not work at such a low clock rate over the full range of voltage and full range of ambient temperature. The ADS5463 does not have a PLL nor a duty cycle correction circuit to impose a lower limit on sample rate, but there are some aspects of the design of the sample and hold circuit in the analog front end that impose the lower sample rate. (There are internal nodes in the device that are pre-biased to a desired level and with too long of a clock period the internal node could droop too far away from the desired pre-bias before the signal is sampled.) The ADC would operate at a lower clock rate, but the analog performance specs listed in the datasheet would no longer be guaranteed. And since the datasheet lists 20Msps as the lower sample rate, the device was not characterized for lower speed operation so I would not be able to tell you how much performance degradation to expect either. Regards, Richard P.
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