Hi Rajashekhar, Welcome to our e2e forum! The digital I/O levels listed in the table on page 3 of the ADS7852 datasheet show 3.0V as the minimum input high level, so the 2.6VOH of the TXCO may not work reliably. You need to be at least at the 3.0V level.
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Forum Post: RE: ADS7852: ADS7852
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Forum Post: RE: ADS8341: ADC Error with External vs Internal Clock
I tried that as well. There is no change in the output. Is the clock pattern correct? Old uC is 8 bit and new one is 32 bit. Is that making any difference?
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Forum Post: RE: TSW14J57EVM: TSW14J56EVM replacement
Hi John, We are pushing older TSW14J56/7 fpga cards to the TSW14J59EVM. Firmware for the J59 would be developed through TI-JESD204-IP request for the specific DAC mode and class of AMD FPGA. Thanks, Chase
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Forum Post: RE: DAC39RF10-SP: Inquiry on how to apply code carrier coherence
JH, We are verifying with our Global Trade Compliance team how we should handle requests coming through a distributor since this device is export controlled. We should have an answer early this week. Regards, Geoff
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Forum Post: RE: TSW14J57EVM: TSW14J56EVM replacement
Hi Chase, Will the TSW14J59EVM be fully compatible with the DAC39J84EVM and DAC38RF82EVM for use with HSDC Pro ? Are there any known limitations or issues with using the TSW14J59EVM to control these DAC evaluation modules? Thanks in advance for your clarification!
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Forum Post: RE: TSW14J57EVM: TSW14J56EVM replacement
The J59 will not work with HSDC Pro. you have to submit IP request and use vivado for control. Hardware wise there may not be 1:1 connections over the FMC connector since J59 does not route all HPIO signals to FPGA banks, but it is best to confirm on schematic. If not, you may have to get creative with how to pass SYNCb in the event you wanted to do cmos syncb or some other case which isn't inherentely supported due to lacking IO pins. Worst case is to use SPI SYNC or SIF SYNC for jesd link during evaluation. Thanks
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Forum Post: RE: ADS1298: DRDY pin not going low although the other functions working well
Hello Khoi, Are you using internal or external clock mode? Only R65 or R60 should be installed, but not both. If you are using external clock mode (OSC1), install R65 and remove R60. If using internal clock mode, install only R60 and ensure that your MCU is pull the pin high to DVDD level. Can you check the clock settings? Regards, Ryan
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Forum Post: AFE4900: afe4500
Part Number: AFE4900 Other Parts Discussed in Thread: AFE4500 Tool/software: Mauser is showing the afe4500 product as obsolete. I am building a medical device. How long will this IC be avqilable? Thanks Marc
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Forum Post: RE: ADS1299-4: About resistance measurement function (LOFF(AC))
Average of the received signal amplitude (Vp) should be ok for calculating the impedance. Regards, Ryan
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Forum Post: RE: ADS1299-4: [Config Support]ADS1299-4 SRBx, BIASx pin configuration
Hello - please refer to our device data sheet and ADS1299EEGFE-PDK User Guide for recommendations on electrode connections, specifically for bias and reference electrodes. Regards, Ryan
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Forum Post: ADS1261: System cycle time calculation at 40k ODR
Part Number: ADS1261 Tool/software: Hi, I am using an ADS1261 designing a force plate with four loadcells, my object is sampling the sensor at 1000hz, according to ads1261's datasheet tab8 and sbaa535a , when I use below parameters, filter type: SINC5, datarate:40000, chopping: disabled, # of channels :4, the calculated system cycle time is: (0.179+2*(1/40)) *4 = 0.916ms. I want to confirm the result, or if there is some wrong calculation, the 1000hz is easy to process for the data analysis. Thanks very much
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Forum Post: RE: ADS1299: Channel Crosstalk in μA Excitation for Lead‑Off Detection
Hello Divya, Please excuse the delay in my response as I was out of office for several days in the past two weeks. The ADS1299 current sources have only a typical ±20% tolerance. Therefore, calibration would be required in order to achieve any reasonably accurate impedance results. Without calibration, I would suggest that they only be used as a method of monitoring gradual change in impedance over time, or simply to monitor ON/OFF status at DC. This article below discusses some techniques which can be used to improve the accuracy of the impedance measurements, especially when using the AC lead-off frequency options. I will highlight a few key points below: Current sources must be calibrated at DC to determine absolute magnitude. The same current sources are used for AC LOFF (alternating INxP and INxN connections). Mid-supply common-mode voltage must always be maintained (VCM = (INxP + INxN)/2). This is to ensure the PGA is operating linearly and the voltages on each input do not force the output to swing too close to AVDD or AVSS. I suspect this can be an issue at higher LOFF current magnitudes. At AC, the data must be adjusted to account for the gain of the digital filter (see datasheet Figure 28). This becomes most important for fDR/4 LOFF frequency. Link to Article: Signal Chain Basics #149: How to accurately measure electrode impedance for lead-off detection in ECG systems - Planet Analog Regards, Ryan
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Forum Post: RE: ADS131M06-Q1: ads131m02
Hi peter, You did not answer my question, where is your input clock to the ADC (pin 23 - XTAL1/CLKIN)? Your schematic does not show it. In your first timing, the /SYNC from your microcontroller was always low, this signal forced the ADC to Reset mode. In your second timing, the ADC did not convert as the /SRDY is always high, the clock may be missed. In your third timing, your tried to read a register but your SPI configuration on your microcontroller was wrong, your were sending commands to the ADC at the rising edge of SCLK, the right edge is falling edge, the SPI setting should be CPOL = 0 and CPHA = 1. BR, Dale
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Forum Post: RE: AFE4900: afe4500
Hi Marc, Thanks for the question. The AFE4500 is not obsolete but is now a custom device. It will continue to be available but the purchasing method has changed. I will email you offline to discuss further. Regards, KD
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Forum Post: RE: ADS1261: System cycle time calculation at 40k ODR
Hi zhaojia, I am not sure where the factor of 2 comes into the equation, unless you are planning on taking 3x measurements per load cell: the first measurement completes in 179us, while the other two measurements complete in 1/40000 = 25us. So that means each load cell is measured in 179 + 25 + 25 = 229us, and then all 4x load cells are measured in 916us, which is what you calculated If these assumptions are correct, then I agree with your calculations -Bryan
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Forum Post: RE: AFE882H1EVM: EVM application usage
Doudu, Can you take a picture of the EVM to show the jumper connections? It may help me debug the output. Do you have the +15V and -15V supplies connected? Joseph Wu
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Forum Post: RE: SN54SC8T541-SEP: Is the Output Current Limit in SN54SC8T541-SEP Datasheet Specified Per Pin or Per Device?
Hello Dhir, Current mentioned on the datasheet is per pin. Regards, Josh
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Forum Post: AFE532A3WEVM: HELP on SMART-DAC-EVM-GUI
Part Number: AFE532A3WEVM Tool/software: After installation on my Window 11 computer, and run Smart-DAC-EVM-GUI, show following error. Error 1003 occurred at Invoke Node in SmartDAC.lvlib:Startup Splash Screen.vi Possible reason(s): LabVIEW: The VI is not executable. This error may occur because the VI is either broken or contains a subVI that LabVIEW cannot locate. Select File>>Open to open the VI and verify that you can run it. VI Path: C:\Program Files (x86)\Texas Instruments\SMART-DAC-EVM-GUI\SMART-DAC-EVM-GUI.exe\Hadron\SW\EVM+\SRC\Main.vi I installed newest version NI LabVIEW runtime engine, same issue. Best, JY
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Forum Post: RE: AFE11612-SEP: Queries Regarding ADC Reference, ENOB, AVcc, and Remote Temperature Inputs
Hi Dhir, These are per I/O pin. I'll talk with a designer about the sequencing issue since the datasheet doesn't specify what could happen. They may be able to run simulations to give a better idea. Thanks, Erin
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Forum Post: RE: AMC131M03-Q1: ads131m04
Hi Srinath, If the device is configured for 24 bit mode, all the words will be in 24 bit format. For the 3 ADC values, it will be a full 24 bit adc data value. For the other words (response and crc), the 16 bit data will be zero padded to the 24 bit length (padding is at the end). Thanks.
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