Hi Michael Kruger, Thanks, this finally worked. To clarify, in all images, the blue/purple signal is DIN (to the ADC) and the yellow/green signal is DOUT (from the ADC), correct? If I read all of the images left to right, top to bottom, this is what I see. Please address any comments I have made: Send the START command RREG for CONFIG2, DRDY is high, int CLK, SYNCOUT disabled, Pulse control mode RREG for CONFIG2, DRDY is low, int CLK, SYNCOUT disabled, Pulse control mode ?? There is no valid command 0x32 - are you sure you are launching/capturing data on the right SCLK edge? DIN is latched into the ADC on the falling SCLK edge RREG for CONFIG2, DRDY is low , int CLK, SYNCOUT disabled, Pulse control mode --> RDATA command, data = 0x3FE77F, checksum = 0x20 Wait for >3ms, then issue another START command RREG for CONFIG2, DRDY is high, ext CLK, SYNCOUT disabled, Gate control mode --> why is the clock now external, and you are in gate control mode? RREG for CONFIG2, DRDY is high, int CLK, SYNCOUT disabled, Pulse control mode RREG for CONFIG2, DRDY is high, ext CLK, SYNCOUT disabled, Pulse control mode --> why is the clock external again? RREG for CONFIG2, DRDY is low , int CLK, SYNCOUT disabled, Pulse control mode --> RDATA command, data = 0x3FE77F, checksum = 0x20 It seems like there is something messed up in your communication, because the settings seem to be changing without you actually doing anything (unless you are performing additional actions and just not capturing them here). Also, the checksum I calculate for 0x3FE77F is 0x40, not 0x20 Please make sure your controller is sending the data to DIN on the appropriate SCLK edge, and that your analyzer is capturing data from DOUT on the appropriate SCLK edge -Bryan
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Forum Post: RE: ADS1259: ADC conversions returning duplicate values.
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Forum Post: RE: ADS1259: ADC conversions returning duplicate values.
Hi Bryan, Yes, unfortunately I see we are having issues with the logic analyzer capturing the traces correctly. So I dont think the settings are changing at all. I will try to recapture it. The original message has the communication as sent and received over SPI as our microcontroller interprets it: SPI Transfer Send Stop Command: Sending: 0x11 Receiving: 0x00 SPI Transfer Initialize Registers: Sending: 0x40 0x08 0x05 0x50 0x10 0x00 0x00 0x00 0x00 0x00 0x40 Receiving: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 SPI Transfer Readback Registers: Sending: 0x20 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Receiving: 0x00 0x00 0x25 0x50 0x10 0x00 0x00 0x00 0x00 0x00 0x40 Start Command: Sending: 0x08 Receiving: 0x00 Check Conversion Finished: Sending: 0x22 0x00 0x00 0x00 Receiving: 0x00 0x00 0x90 0x00 Sending: 0x22 0x00 0x00 0x00 Receiving: 0x00 0x00 0x90 0x00 Sending: 0x22 0x00 0x00 0x00 Receiving: 0x00 0x00 0x90 0x00 Sending: 0x22 0x00 0x00 0x00 Receiving: 0x00 0x00 0x10 0x00 Read Data: Sending: 0x12 0x00 0x00 0x00 0x00 Receiving: 0x00 0x3F 0xC7 0xA3 0x44 Start Command: Sending: 0x08 Receiving: 0x3F Check Conversion Finished Sending: 0x22 0x00 0x00 0x00 Receiving: 0xC7 0xA3 0x90 0x00 Sending: 0x22 0x00 0x00 0x00 Receiving: 0x00 0x00 0x90 0x00 Sending: 0x22 0x00 0x00 0x00 Receiving: 0x00 0x00 0x90 0x00 Sending: 0x22 0x00 0x00 0x00 Receiving: 0x00 0x00 0x10 0x00 Read Data Sending: 0x12 0x00 0x00 0x00 0x00 Receiving: 0x00 0x3F 0xC7 0xA3 0x44
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Forum Post: DAC38J84: Is SYNCb used?
Part Number: DAC38J84 Tool/software: In the DAC38J84 specification, it is mentioned that only JESD204B subclass 1 is supported. Since the SYNCb signal is exclusively used by subclass 2, does this mean that this signal and all related configurations are currently unused? Additionally, in config72 , bits 3:1 allow selecting the JESD204B subclass, but as i mentioned, the documentation states that only subclass 1 is supported. Does this imply that the DAC38J84 was initially designed to support all three JESD204B subclasses, but at some point, this was discontinued? For instance, were signals like SYNCb (used by subclass 2) left with no functionality in the final implementation? I find this a bit confusing and would appreciate clarification.
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Forum Post: RE: LM98725: PGA gain of LM98725
Hello Katagiri-san, Unfortunately, we don't have the data. Information we can provide you is datasheet specification only. BR, Norikazu
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Forum Post: RE: ADS7142: Offset Calibration Issue
Hi Lane, Hopefully we can rule out issues with the I2C communications before concluding there is something wrong with the device, though it is strange that you are seeing such a large offset after powerup. Bear with me for the following questions, but the answers will help out greatly. 1. How are you determining the magnitude of the offset calibration error? Are you shorting the input to ground, or giving it a known voltage at the input? How are you reading the conversion value back? In manual mode, high precision mode, or other? 2. Is it possible that there are any addressing conflicts with the I2C devices? Does every I2C device on the bus have a unique 7-bit address, and are you able to individually address the I2C devices and see a response from each of them? 3. Do you have logic captures you can share showing a normal register write and subsequent readback of the updated register value? SCL, SDA, and the BUSY line should be included in this. 4. Can you share an oscilloscope capture of AVDD on startup? It might be possible that the device does calibrate before AVDD is at its final value, and after AVDD settles, the offset compensation value is outdated. Regards, Joel
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Forum Post: RE: ADC3669EVM:Data corruption - ADC3669EVM
Hi Robert, Kindly confirm if you are carrying out some form of IO calibration in order to meet timing at 400MHz (800Mbps). Your data corruption issue seems to indicate that there is a bit slip on some of the lanes, which is dependent on the capture architecture. This can happen during IO calibration (if each data lane is tuned independently and lanes correct in a way that they are skewed by a bit). In addition if you are using SERDES instances, the the reset to the SERDES of all the lanes should be synchronously de-asserted (else the de-serialization counters can be out of sync). If you are doing neither and just using IDDR elements (possibly in same_edge mode), then it does seem to point to a timing issue. Does the issue get corrected if you slow down the clock rate? Regards, Ameet
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Forum Post: RE: ADS7128: ADS7128 rms module
Hi Alex, TI offers many M0/M0+ options, notably the MSPM0 family of MCUs. For MCU suggestions, can you post on the Arm-based microcontrollers E2E forum ? My team will follow up with 2-channel, 16-bit ADC options here. Regards, Joel
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Forum Post: RE: ADS1675: Strange behavior with warmed-up component
Hello Soeren, The ADS1675 AVDD current is about 70mA. If you have other components powered from the 5V supply, then these will add to the total current. There is no over-temp specification for the LP2992 that I can find, but these are typically set around 170C. Based on the thermal specs of the SOT23 (DBV) package, 1W of power dissipation in the LP2992 will likely cause over-temperature shutdown. Assuming you have other loads on the AVDD 5V supply increasing total current load to 100mA, then a 15V input voltage would result in about 1W of power dissipation, which would be enough to put the regulator into over-temperature mode. Regards, Keith
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Forum Post: RE: ADS1259: ADC conversions returning duplicate values.
Hi Michael Kruger, Thanks for clarifying There is no clear reason why the ADC would read back the same data, unless of course the conversion didn't actually restart (though this is inconsistent with the DRDY behavior) Can you probe the DRDY pin to see if this pin follows the same behavior as the DRDY bit in CONFIG2? Can you try controlling conversions with the START pin instead of the START command to see if that changes the behavior? What SCLK and CLK speeds are you are using? I assume START is tied low, and RESET/PWDN are pulled high? Is the next read after the duplicate always new data? You said this can happen "a few times in a row", so does that mean you can read the same value more than one additional time? Can you be more explicit about how often (does every read get repeated, just certain ones?) and how many repeated data there are? Can you reproduce this issue on your end? It seems like you have gotten systems back from the field that have this issue, but have you had any luck reproducing it on a known good system in your lab for example? Does this issue happen randomly, or is there any discernible pattern to it? An alternative solution to this issue would be to just ignore identical data points during this stabilization period i.e. any time the difference = 0, something is wrong -Bryan
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Forum Post: RE: ADS8689: help regarding flexible AFE 0-10V/4-20mA
Hi Jonas, Unfortunately the author of TIDA-01333 has left the company. Using a high value pullup to detect open wire is fine. For C44, compare the schematic to the text - C43 is the bypass cap on the OPA192. I believe that note is actually referring to C44, not C43.
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Forum Post: RE: ADS8689: 800Vdc measurement
Hi Ludwig, Unfortunately no, it is not possible to shut off the bias or bypass the internal LPF. I asked about the buffer since I thought that might be easier on you versus swapping out the ADC and changing your software to accommodate a different part. Speaking of which, the ADS8509 might be an option for you if you want to try a different ADC. That part using pin strapping to get a +/-10V input range on a single 5V supply.
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Forum Post: RE: DAC082S085: DAC not able update voltage
Hi Akanksha, Update the data on the rising edge of SCLCK, not the falling edge. Best, Katlynne Jones
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Forum Post: RE: ADS7138-Q1: Reading analog inputs
Hi Joel, Good info. We have a Total Phase Beagle. I'll try capture the communications. Thanks, Titngai
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Forum Post: RE: ADC12QJ1600-SEP: Interface to Microchip Polarfire FPGA JESD204B configuration (8 Lanes)
Hi Eric, I provided all the data I can, please acknowledge and let me know your thoughts. Thanks Madhu
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Forum Post: RE: ADS8355: Ads8355
Hello Karunakaran, Welcome to the E2E forum! At the moment we do not have sample code or guidelines for the ADS8355. The C2000 development page does have some resources that could help to start with. Depending on the type of project you had in mind for the ADS8355 there could be some reference designs that are already implementing some of the resources available for the C2000, like the TIDA-00176 . Best regards, Yolanda
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Forum Post: RE: DAC38J84: Is SYNCb used?
Hi Pablo, In general, all JESD204B subclasses need the physical SYNC signal. The below sentence is not a correct understanding [quote userid="639344" url="~/support/data-converters-group/data-converters/f/data-converters-forum/1464913/dac38j84-is-syncb-used"]Since the SYNCb signal is exclusively used by subclass 2, does this mean that this signal and all related configurations are currently unused?[/quote] DAC38J84 only supports subclass 1, basically using SYSREF to synchronize the LMFS.
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Forum Post: TPL0102-100: Tpl0102 dual supply operation
Part Number: TPL0102-100 Tool/software: Hello, I am using dual supply operation of TPL0102. Can I use it like this, as given at the below scheme? I need to get -2V to 0V from Wa and Wb. Regards, Eren Yildiz
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Forum Post: RE: ADC12QJ1600-SEP: Interface to Microchip Polarfire FPGA JESD204B configuration (8 Lanes)
Hi Madhu, The JESDV value of 2 is actually accurate, considering this is a JESD204c compatible device. The value of 1 listed in the datasheet is probably a typo (we will check regarding the same). Please let me know if you are having link bringup errors. In general, a mismatch between the Tx and Rx ILA parameters does not prevent the link from coming up, as the standard does not mandate that they need to match (unless the Rx IP has been configured to abier on an ILA mismatch). Regards, Ameet
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Forum Post: RE: TLV2548: TLV2548IPW
Hi Ivy, Typically in the case of three-phase current measurement, we see more simultaneous-sampling ADCs in use over multiplexed ADCs such as this one, as it is important to sample all three phases at the same time, or there will be a phase shift introduced into the measurement. Generally, since this is an older device, I would recommend the ADS131M08 for an 8-channel, simultaneous-sampling solution. There are also fewer channel variants if that is more suitable. If you would like to stick with a multiplexed ADC, then the ADS7038 is the newer device recommended to replace the TLV2548. At what stage are you in your design, and would these suggestions above fit your requirements more closely? Regards, Joel
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Forum Post: RE: TPL0102-100: Tpl0102 dual supply operation
Hi Eren, The device will act as a voltage divider with the wiper output ranging from HA to LA. You will not get the full 8-bits of resolution because you are not using the full range, but yes, you can use the device as shown in your circuit. Make sure your I2C controller will work with 2.5V logic. Best, Katlynne Jones
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