HI Sahar, That wouldn't hurt to see. Go ahead and send the screenshot in case there is any information to gather from it. Regards, Joel
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Forum Post: RE: BP-ADS7128: USB Port not detected
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Forum Post: RE: BP-ADS7128: USB Port not detected
hi Joel, Here is a partial preview of it. I will also upload the voltages for the ADS7128 pinouts as it's connected to the MSP432 launchpad. Just gotta edit the image for it a bit.
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Forum Post: RE: ADS1115: Fluctuations and Offset Errors in Single-Ended Mode with ADS1115.
Hi Athulya, [quote userid="632064" url="~/support/data-converters-group/data-converters/f/data-converters-forum/1441558/ads1115-fluctuations-and-offset-errors-in-single-ended-mode-with-ads1115"]to measure current changes across an AC load using a CT sensor. [/quote] You seem to be describing an AC application. The ADS1115 is typically intended to measure DC / slow-moving signals. The max output data rate offered by the ADS1115 is 860SPS. Using the max data rate available, for detecting a 60Hz signal, you would only get about 14 samples per cycle of your waveform. This is more than likely not enough for your application, and won't get a good recreation of the input signal. You might want to consider using a different ADC that is meant for these types of AC applications, such as the ADS131M0x family of devices: ADS131M04 data sheet, product information and support | TI.com [quote userid="632064" url="~/support/data-converters-group/data-converters/f/data-converters-forum/1441558/ads1115-fluctuations-and-offset-errors-in-single-ended-mode-with-ads1115"]the formula used to convert the ADC value is voltage = ((adc_value * FSR * 1000) / 32768)[/quote] The voltage value is calculated by multiplying the output code, when converted from binary to decimal, times the LSB size corresponding to the FSR configuration. Voltage value = adc_value (in decimal) * LSB size [quote userid="632064" url="~/support/data-converters-group/data-converters/f/data-converters-forum/1441558/ads1115-fluctuations-and-offset-errors-in-single-ended-mode-with-ads1115"] Comp_que : Set to 00 (no comparator)[/quote] '11' would be what disables the comparator. '00' asserts the alert pin after one conversion when the output is not within your lo-thresh / hi_thresh register settings. [quote userid="632064" url="~/support/data-converters-group/data-converters/f/data-converters-forum/1441558/ads1115-fluctuations-and-offset-errors-in-single-ended-mode-with-ads1115"]Offset Readings[/quote] Offset measurements are performed by tying the inputs together for the differential measurements, and shorting the inputs to GND for the single-ended measurements. Is this what you are doing to measure offset, or are the inputs simply being left floating? [quote userid="632064" url="~/support/data-converters-group/data-converters/f/data-converters-forum/1441558/ads1115-fluctuations-and-offset-errors-in-single-ended-mode-with-ads1115"]When I switch to differential mode (AINP = AIN0, AINN = AIN3), the ADC shows stable and correct readings: 1.653V when applying the input voltage[/quote] From your drawing, the output of the voltage divider is connected to AIN0, but AIN3 seems to be left floating. Can you clarify what are the actual input voltages at the input pins for your different MUX configurations? Best Regards, Angel
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Forum Post: RE: BP-ADS7128: USB Port not detected
here are the pinout readings. the 0V readings are between 0.01 and 0.018V referencing TP6: edit: the lower row on the analog pins all read at around 0V
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Forum Post: RE: ADC3669EVM: Schematics
Hi Jiri, Can you please send me a picture of the EVM? There are a few different revisions already, I want to make sure you get the correct rev. Thanks, Rob
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Forum Post: ADC08L060: Clock input voltage/sensitivity for VDR=1.8V?
Part Number: ADC08L060 Tool/software: I plan to interface with a 1.8V FPGA for the 8-bit digital output (VDR=1.8V and VA=3.3V). However, it is not clear if the device can accept a 1.8V input on the clock. Table 1 shows the clock input referenced to VA (3.3V) and the converter electrical specs do not specify VIH(min) for VDR=1.8V
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Forum Post: RE: ADC08L060: Clock input voltage/sensitivity for VDR=1.8V?
Hi Canyon, This is a older device, so you need to use 3.3V logic unfortunately, 1.8V from an FPGA won't work. Also, see the limits here in the datasheet: Regards, Rob
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Forum Post: RE: TSC2007: I2C pin level at POR
What I would like to know is, does the pull-up power supply have to be the same as Vdd?
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Forum Post: RE: ADS7865: Power-up sequnce/down sequence
Hello Yolanda, Thanks for your reply. What is the reason for your recommendation? What could happen if BVdd is powered up before/powered down after AVdd? Regards, Satoshi Obata
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Forum Post: ADC12DJ5200RFEVM: Inquiry about Error Messages Related to ADC12DJ5200RFEVM Settings
Part Number: ADC12DJ5200RFEVM Tool/software: Hi Team Could you please assist with the AD12DJ5200RF EVM setup and the related error? Below is a screenshot of the TSW14J59 GUI error message. EVM B/D TEST setup 1. Sampling Clock : 3.93216GHz 2. Ref Clock : 245,76MHz 3. Input : 225MHz - ADCxxDJxx00RF EVM GUI setup 1. Clock Source : External Clock 2. External Fs Selection : 3932.16MHz 3. Sampling and Calibration Mode : JMODE 60 4. EVM Sequence calibration Bset Regards KB
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Forum Post: RE: ADS124S08EVM: Can not read the result under single shot mode using the ADS124S08evm
Hi Bryan, Currently i am limited to install the software for logic analyzer, already to ask it to approve that. The only difference is the mode i set in the GUI. While i cannot get the result in single shot mode. i will try your configuration and obverse the communication by oscilloscope. Matthew
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Forum Post: ADS127L11: Differential OPAMP suggestion
Part Number: ADS127L11 Tool/software: Hello, We are planning to use ADS127L11 in our new design. Input signal bandwidth 0.1HZ - 50KHZ. We are looking for low noise fully differential amplifier. Can TI experts suggest which OPAMP potentially we can use? Thank you for all your support. Regards, Iouri
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Forum Post: RE: AFE58JD48EVM: How to Change LMK Clock rate
We need 5GBPS because, our transceivers works only at 5GBPS, so we want to test our transceivers at 5GBPS.
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Forum Post: ADS124S08: Use the ADS124S08 to replace AD1248
Part Number: ADS124S08 Other Parts Discussed in Thread: ADS1248 Tool/software: HI sir I upgrade the parts from ADS1248 To ADS124S08 old design ADS1248 use +2.5v for VDD, -2.5V for VSS ADS124S08 can accept the same dual power,postive/negative? thanks or did you have any guide? ADS1248 Change to ADS124S08?
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Forum Post: RE: AFE881H1: WDT Feeding During SPI Write Failure Conditions Caused by HART Transmission
Shunsuke-san, I did have a chance to try the double write where the WDT initialization is done and then the WDT is enabled. When I tried it, it caused the device to give the alarm. I'm going to check my code to make sure the initialization was done properly, but for now, I do not think it works. I just wanted to let you know. I'll try a couple of other versions of initialization for testing soon. Joseph Wu
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Forum Post: DDC3256: ADC DDC3256
Part Number: DDC3256 Tool/software: Hi TI, I have some issues with ADC DDC3256 when sending config via SPI. 1. This is my schematic with ADC DD3256. + Pin TP_SEL to GND + AVDD to 1.85 V + VRef to 1.25 2. Send command reset with addr = 0x00 , data 0x0003, But pin SDOUT of ADC DDC3256 not response , it's always level high. 3. Send command set Page Select = 1 with addr = 0x03 , data = 0x0002, But pin SDOUT of ADC DDC3256 not response , it's always level high. 4. and send command read addr = 0x03 But pin SDOUT of ADC DDC3256 does not respond, it's always level high. ==> I don't know, why ADC DDC3256 not response to all commands sent via SPI config. who can help me with this? Thanks
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Forum Post: RE: Excess THD in DAC8822 circuit used as audio DAC
Hello Paul, thank you for your suggestions. Alas, they didn't work. I also tried to halve the reference voltage to check whether the THD is generated in the I/V converter opamp due to the large voltage swing. The result was actually an increase in the THD. I'm beginning to think that the problem is related to the DAC's DNL or full-scale error. I also checked the supplies and the reference voltage when the DAC is delivering 0dBFS: all three show the same harmonics and spurs content as the signal, but not the fundamental. Could it be a ground problem? My testboard has a solid ground plane on the bottom layer, all grounds refer to it, but not as a star.
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Forum Post: ADS124S08: Issue with noise performance between REF0 and REF1 when reading RTDs
Part Number: ADS124S08 Tool/software: Hello, Me and my team are currently working on a product that reads out multiple RTDs (PT1000) in a sensor array. Our target accuracy is to measure steps of 10mK at a rate of 10 samples per second. We use 2 input channels on the ADS124S08 with a 4 wire configuration. Each input channel has a set of multiplexers connected that shift through a series of 16 RTDs. For this reason we can only measure in single shot conversion mode and we need at least 400SPS to read out all sensors 10 times per second. Each of the 2 channels is configured with its own reference resistor (0.01% accuracy) . Multiple copies of this circuit are used on the same board to read out several hundreds of sensors at once. We’re very pleased to see that the noise performance on all RTDs connected to REF1 is within the expected range. However all sensors connected to REF0 are doing much worse. Settings for each channel are set up identically. Figure shows 8x sensor connected to REF1 (Left) vs REF0 (Right) When swapping sensors but keeping everything else the same the problem remains on the channel that uses REF0. Component values for each circuit are identical and the board layout is set up symmetrically as much as possible. There where it is not possible to use a symmetrical layout the traces of the REF1 circuit are all longer. Registers set to configure the ADC. Register value CH1 Note IC1 Register value CH2 Note IC2 General note ID 0x08 0x08 STATUS 0x80 0x80 INPMUX 0x12 MUXN = AIN1 MUXP = AIN2 0x34 MUXN = AIN3 MUXP = AIN4 PGA 0x68 0x68 256 * tMOD PGA enabled PGA gain = 1 DATARATE 0x39 0x39 Low-latency filter Single-shot conversion mode 400SPS REF 0x15 REFP1, REFN1 0x11 REFP0, REFN0 REFP_BUF enabled REFN_BUF disabled Internal reference on, but powers down in power down mode IDACCMAG 0x45 0x45 PSW closed 500 muA IDACMUX 0x0C 0x0C I1MUX = AINCOM I2MUX = AIN0 VBIAS 0x00 0x00 SYS 0x10 0x10 OFCAL0 0x00 0x00 OFCAL1 0x00 0x00 OFCAL2 0x00 0x00 FSCAL0 0x00 0x00 FSCAL1 0x00 0x00 FSCAL2 0x40 0x40 GPIODAT 0x00 0x00 GPIOCON 0x00 0x00 The design is based on application notes sbaa275a and sbaa201a and the IC is connected as follows: We do not understand the big difference in noise performance between the two channels. Since all of the hardware is identical and all the settings are triple checked at this point I don’t know where to look anymore to explain the difference. Can anyone point us in the right direction? Kind regards, Berrie
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Forum Post: RE: DAC43204: I2C about DAC43204 and CG5162
Hi Katlynne, Can the issue occur if the host reads data from the DAC and light sensor without ACK when receiving data? Thanks Hector
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Forum Post: RE: ADS1018-Q1: question about Vin clamp voltage in different FSR
thanks
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