Part Number: TLA2528 Tool/software: Hello, I am going crazy when trying to read adc values from TLA2528. The I2C single register read and write is fine. I set the FIX_PAT_ENABLE flag on register DATA_CFG and I expect to read 0xA5A but I get 0xFFA5. I have set the capture in MANUAL MODE. The read of the STATUS REGISTER returns 0x80. Moreover, if I have correctly understood the Datasheet on 7.4.2, after a 2-byte frame, the next 2 bytes will provide a new frame. In my case when I read 4 bytes, I get 0xFFA5FFFF. The 0xFF on the frames are also well visible in the scope signal. This is the code I use to read the channel data: uint16_t TLA2528_read_one_channel_data ( uint8_t channel_num) { err_t ret; uint16_t dataread = 0; uint32_t datareadt = 0; i2c_cmd_handle_t cmd = i2c_cmd_link_create (); i2c_master_start (cmd); i2c_master_write_byte (cmd, (m_TLA2528_address << 1 ) | READ_BIT, ACK_CHECK_EN); i2c_master_read (cmd, ( uint8_t *)&datareadt, 2, ACK_CHECK_EN); i2c_master_stop (cmd); ret = i2c_master_cmd_begin (I2C_MASTER_NUM, cmd, 100 / portTICK_PERIOD_MS); i2c_cmd_link_delete (cmd); dataread = ( uint16_t )datareadt; return dataread; } If I disable the FIX_PAT_ENABLE I get values which corresponds with the input voltage but always in one byte while the second byte is 0xFF. What is wrong with my code? Thank you
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Forum Post: TLA2528: TLA2528
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Forum Post: RE: ADC12DJ5200RFEVM: JESD204B Mode 61, A & B link FMC routing
Hello Jeff, Unfortunately there is no way to map the B channel lanes to the an A channel output. There are registers to power down the separate channels of A and B which will also shut down the JESD subsystem for that channel. These are default turned off and in this particular mode (61) I would not recommend doing this as it is an interleaved mode. One important note is that on the ADC12DJ5200RF EVM all of the B channel JESD lanes are inverted going to the FMC which is something you will have to account for in your FPGA FW. Additionally, if you would like we do offer custom JESD reference designs to enable fast prototyping on the FPGA side. These designs will be custom for the ADC and mode of operation you choose. If this is something you would be interested in please let me know. Best, Eric Kleckner
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Forum Post: TI-JESD204-IP: TI JESD204C IP simulation issue
Part Number: TI-JESD204-IP Tool/software: Hello, I'm trying to run a simulation in Vivado with the TI JESD204C IP TX and RX cores back-to-back and am seeing that the rx_all_lanes_locked signal out of the RX core (as well as TX) is always 'Z'. I am following the recommended reset procedure and have checked that I'm not doing something dumb with signal assignments. Can you think of anything that would be causing this issue? Thanks!
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Forum Post: RE: ADS54J40: Inquiry on how to calculate overall latency of ADS54J40
Hi JH, Can you provide some additional details on the customer's configuration? The TX delay is dependent on a few factors including Sampling Rate, Interface Rate, and JESD Lane rate. Once we have this information, the design team will be able to provide a TX delay. Best, Luke Allen
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Forum Post: TX7332EVM: GUI operating system compatibility
Part Number: TX7332EVM Other Parts Discussed in Thread: TX7332 Tool/software: I have followed the steps to install the TX7332 EVM GUI on a machine running Windows 11. However, when it reaches the startup splash screen it hangs on the "Loading Main.vi..." step. Does this indicate that the GUI is not compatible with Windows 11? The additional programs (Python, Labview, Windows .NET) are all installed.
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Forum Post: RE: ADS1298: isolation protection circuit
Hi Avvaru, Thanks for clarifying. Generally such protection circuitry consists of transient voltage suppression (TVS) diodes and high-power current-limiting resistors. For legal reasons, we cannot provide specific isolation protection circuitry for patient safety. Regards, Ryan
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Forum Post: RE: ADS131M04: N-pin voltage refers to communication issues
Hi wei, It seems you uploaded some images, but failed. Please upload them again. I hope these are timing plots which will be helpful to address your register reading issue. BR, Dale
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Forum Post: RE: ADS1298: Simulation of ADS1298
Hello Varun, Thank you for your interest in our ADS1298. Unfortunately, we do not offer a PSpice or TINA-TI model for our ADS1298 since it is a complex device with an input PGA, RLD feedback amplifier, lead-off detection current sources and comparators, etc. Is there a specific portion of the device you are interested in modeling? For the PGA stage, the OPA350 has similar input impedance and bandwidth characteristics, which could be used as a first-order approximation of the input stage in the ADS1298. Regards, Ryan
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Forum Post: RE: ADS1220EVM: Can't Manually install the ADS1220EVM plugin in ADCpro
Hi Timo Zellmer , This appears to be a Windows file-permissions error that is preventing the installer from copying files from one location to another. However, this is not a critical step as these files are not used to run the application, and installer appears to be aborting after the main installation has completed. I don't believe this error will prevent you from using the application since the installer did not perform a rollback operation. Have you attempt to run the GUI after this error occurred? While we should look into correcting the issue with the installer, I think the GUI should work even with this issue. Please let us know if this is the case or not! Thank you, Chris
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Forum Post: RE: DAC82001: Output noise (0.1 - 10Hz) graph
Hi Sato-san, This delay is from an internal T/H deglitcher on the device. The delay is created from a RC time constant, ideally 200 ns. Typically, it would have 10% accuracy or +/-20 ns. The maximum variation would be 30% accuracy, or +/- 60 ns. I personally have seen very little variation on the EVM. Thanks, Lucas
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Forum Post: RE: ADS8686S: Bandwidth using Oversampling
Hi Cornelius, The speed of data stream to the digital filter inside the ADS8686S ADC is always 1Msps (sampling rate) whether the internal multiplexer is switching or not, so your sampling rate should not be divided by the number of channels (e.g. 1Msps/8=125ksps) in your calculation. I did the following calculation and analysis for you: As you can see from the analysis table above, the output date rate (ODR) are calculated based on the acquisition time and conversion time under different OSR configurations, these are the actual data speed shifted out by the ADC and can be seen by your microcontroller. The bandwidth (BW) of digital filter can be calculated with ODR/(1+the order of filter) as a common approach, the order of the SINC filter in ADS8688S is 2,so the BW for every OSR configuration can be calculated as shown in the table above. I also listed the BW of the internal analog LPF in ADS8686S, so the yellow boxes in the table show the dominated BW of the whole signal chain under the specified OSR configuration. As you can see, t he dominated BW in yellow match the specified BW of the digital filter in blue which are shown in the table 7-3 in ADS8686S datasheet . I hope my calculation and explanation can help you understand well. Best regards, Dale Li
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Forum Post: ADS1256: Electromagnetic interference
Part Number: ADS1256 Tool/software: Hi Team, I have developed a board with the ADC mentioned. The ADC is about 8 cm from another board (same reference) in which a 5nF capacitor is discharged through a 3MΩ resistance. The voltage stored in this capacitor is 5kV. This system has been in production for about 1 year without any detected problems until now. The last boards produced are experiencing an issue related to the ADC. The ADC is powered by a 5V regulator for its analog section and a 3.3V regulator for its digital section. When the discharge occurs, the 3.3V digital regulator (which has an internal limit of 100mA) drops to approximately 2V. The 5V analog section remains unaffected. I have found that the ADC is causing this issue. If I change the discharge resistance to 150MΩ (The discharge resistance must be < 3MΩ ), the problem does not occur. This issue has never happened before. Could you help me with this?
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Forum Post: RE: ADC12DJ5200RF: JESD204C AND SERIALIZER LATENCY from ADC12DJ5200RF Datasheet
Hello Ziquan, I am a little bit confused what you are trying to accomplish can you please clarify your question a bit. The deterministic latency is of a JESD system is found by finding your worst case delay for a given system and then setting your release buffer delay value on your receiver to ensure that you never violate this delay. Best, Eric
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Forum Post: RE: ADC12DJ5200RFEVM: Diagrams in ADCxxDJxx00RF Evaluation Module User's Guide
Hello Makoto, Q1. Yes this is correct. Q2. They are not enabled by default as it is not a requirement because all clocks are derived from a single source in both cases actually and do not have to be synchronized. Q3. The signal you highlight is not a sysref signal it is the reference clock for all the other clocks to be derived from. In on board clocking mode it comes from a clock synthesizer LMK61E2, in external reference mode it comes from an external signal generator. Q4. I don't understand this question in both modes of operation the reference clock for the LMX2594 is derived from oscin of the LMK00304, all this chip does is buffer the input clock to both the LMK04828 and LMX2594. Q5. This is an external JESD sync that can be used for debug, but by default you should use sync from the FPGA for operating the JESD link. best, Eric
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Forum Post: RE: ADC12DJ5200RF: JESD204 LINK from ADC12DJ5200RF Datasheet
Hello Makoto, Q1. Yes each link transmits data in sync. Q2. If you are not using these lanes you can leave them disconnected. best, Eric
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Forum Post: RE: ADC12DJ5200RF: Device clock calculation
Hello Makoto, For operation of the ADC in JMODE 0 the effective sampling rate of the converter is double what you apply at the input as this is an interleaved mode of operation. So in your case you if you sample clock is 2GHz your effective sampling rate will be 4 GHz, but you will only get one channels worth of data. Best, Eric
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Forum Post: RE: ADC34J24: CDCLVP1204 interface ADC34J24 SYNC
hi Rob, I ended up using a biased three resistor voltage divider to set the proper terminating voltage and common mode voltage to the ADC34J24.
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Forum Post: RE: DAC12DL3200: Biasing the outputs
Hi Charan, Its not that straight forward to recommend a specific value. Since you will be DC coupling and using the LMH amp for the level shift you will need to simulate a value that will work first. Then when you put the values on the board, you may need to iterate slightly. Thx, Rob
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Forum Post: RE: DAC53608: Design Tool for Output Voltage Adjustment using a DAC - SLVC780; positive and negative voltage application
Happy Friday Katlynne, Thanks for your explanation, I think it makes sense though it's not very obvious. Have a good long weekend! Ed
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Forum Post: RE: ADS1256: Electromagnetic interference
Hi Lucas Rosa, Some questions for you: Can you help us understand how you determined the ADC is causing this issue? It sounds like the discharge is causing this issue, which is negatively affecting the ADC and surrounding circuitry. Also, the ADC can work down to AVDD = 1.8V, so an LDO at 2V would not necessarily be an issue for the ADC When you say the boards have the "same reference", does this mean that there is a voltage reference on one of the boards that is used for both (the ADC and maybe some other circuit)? Or is "reference" in this case referring to the ground i.e. the boards share the same ground reference? How do you recover from this issue? Do you have to power cycle the boards? Or does the digital LDO return to 3.3V once the cap has finished discharging? Is the cap discharging into the same ground as the ADC? Or do you have something like a PCB ground and an earth ground, where the ADC is connected to the PCB ground and the cap discharges to earth ground? Can you provide a schematic of both boards? -Bryan
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