Thanks..
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Forum Post: RE: ADS1120: ADS1120
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Forum Post: RE: ADC3683: Power on/reset calibration and datasheet INL test setup
Hi Drew, Just looking through the code I have I see some configuration error where the output bit mapping is never set due to an incorrect E-Fuse address. Currently the code does: 0x0 <= 1 (if set to reset the device, this line is commented out during the 5 runs I did not rest the device) wait 0x07 <= 0x2B 0x07 <= 0x01 (the address is wrong here should be 0x13 for E-Fuse) wait 0x07 <= 0x00 0x1B <= 0x80 scanning through the datasheet I can't see what the default output mapping is, presumably "001: 2-wire, 18 and 14-bit" or we would not get valid data. This code runs at the start of every experimental run.
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Forum Post: ADS1298R: Rapid baseline transients on the signal on ECG applications - is it RLD ?
Part Number: ADS1298R Dear all, I am designing an ECG device which is using metal electrodes (the resistance is much higher than gel electrodes). Also, the circuit embeds a defibrillation protection circuit between the electrode and the anti-aliasing filters (see. circuit attached). The used values are those from the evaluation board for anti-aliasing filters (two RC filters in a row :10kohm+47pF and 22.1kohm+47pF) and RLD (1Mohm // 1.5nF). When the contact is getting slightly poorer between the electrode and the patient, the baseline is moving extremely quickly and the ECG becomes uninterpretable. Please note that the slow baseline drift will be corrected in software and is NOT an issue at all. I suspect the RLD : do you also share this feeling ? If so, would you decrease the R and/or C value to accelerate the response ? How much ? Thank you, Paul-Alexandre,
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Forum Post: ADC12DL3200: Biasing the inputs
Part Number: ADC12DL3200 Hi, I am using ADC12DL3200 part in my custom design. ADC gets input signal (of bandwidth DC to 750MHz) from a demodulator, so I can only use DC couple interface. Demodulator output has a bias voltage of 0.9V, but the input common-mode voltage of ADC12DL3200 is 0V. So I am using resistive translation circuit as given below Please confirm if the values given are proper. (Considering Current of 10mA). Thanks in advance
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Forum Post: RE: TSW14J58EVM: TSW12QJ1600EVM interfacing with TSW14J58EVM having a issue with Capturing the Data
Madhu, As confirmed yesterday the J19 shunt needed to be removed in order to communicate through the USB port of the EVM as stated in the users guide. I will close the post. Please open a separate post for any future questions. Regards, Geoff
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Forum Post: RE: ADS4146: CLKOUT(CMOS MODE)
Hi, There is no way to tell if the clock is getting full amplitude as either the ground for the probe is not good or has too long a lead causing an inductive loop. Also, what is the bandwidth of the probe you are using for the measurement? Regards, Geoff
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Forum Post: ADS1258: ADS1258 working
Part Number: ADS1258 Hi I am working out interface with ADS1258 with my controller, I am using internal SPI. tracing only SPI working and initializing look like works ok. But I am not able to read channel. My application is to read all 16 channel one by one at 1k sps. below is the schematic. Let me know where I am wrong.
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Forum Post: ADS1220EVM: Can't Manually install the ADS1220EVM plugin in ADCpro
Part Number: ADS1220EVM Other Parts Discussed in Thread: ADS1220 , ADCPRO , Hey there, i am trying to use the ADS1220 Eval board software. The installion of the ADCpro Software worked fine, no issues. But when i want to install the ADS1220EVM plugin i get the following error: After closing the installer, another error appears: After ignorierung the message, i get the following files in the installation folder (only temp folder, no ADS1220): All the installions were executed as administrator. Does anybody what may cause this issue? Best regards Timo
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Forum Post: RE: ADS8688: ADC gives spikes and dips randomly
Hi Vijaya, You mentioned that there is no signal applied to the input. Are the inputs shorted to ground or floating? It looks like you are commanding Manual CH6 operation, does this same issue happen with the other channels? Can you verify that the reference voltage is correct?
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Forum Post: RE: ADS54J40: Inquiry on how to calculate overall latency of ADS54J40
Hi JH, Happy to help. We have reached out to the design team to get either the TX delay or the S2SO latency, please allow us a few days to follow up. Best, Luke Allen
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Forum Post: RE: ADS1298R: Rapid baseline transients on the signal on ECG applications - is it RLD ?
Dear Ryan Thanks for the answer I'll give it a try tomorrow Regarding INxP, they are connected to electrodes as in the evalboard INxN are mostly connected to WCT apart from those who generate Lead I and Lead II. I suppose you refer to Figures 94 and 95 when you say " Are the INxP electrodes selected for RLD common-mode derivation?" Common-mode is set using RL electrode so no INxP electrode is selected for Common-mode derivation. Thank you Paul-Alexandre
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Forum Post: RE: ADS1298R: Rapid baseline transients on the signal on ECG applications - is it RLD ?
Hi Paul-Alexandre, I was referring to Figure 43. This is where the input electrodes are connected to the RLD amplifier inverting input through a summing network. This allows the RLD amplifier to drive a common-mode cancellation signal back to the body. The RLD output would still contain the DC bias voltage present on the non-inverting input. Let me know how the testing goes! Regards, Ryan
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Forum Post: RE: ADC3683: Power on/reset calibration and datasheet INL test setup
Hi, After changing that address to 0x13 and running the efuse, has that changed anything or are you still seeing the same results? Best regards, Drew
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Forum Post: RE: DAC43401-Q1: Want to know the right register for my situation
Hello, The frequency of the square wave is determined by the SLEW_RATE field per this equation: You have left the SLEW_RATE field at the default, so you should update that field to get the frequency you require. The duty cycle is fixed to 50%. The rest of your settings look correct. If you would like more frequency options, or a duty cycle other than 50% you will need to make a modification to your schematic, but if this is the case, the amplitude of the square wave will be fixed from 0 to DAC_SPAN instead of MARGIN_LOW to MARGIN_HIGH. Best, Katlynne Jones
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Forum Post: RE: TPL0102-100: Potentiometer and a timer
Hi Farzaneh, To start, pretty much all of our digital potentiometers have an input voltage range of ~0 to 5V. Some have a negative range such as the TPL0102-100 that you linked. You would need to first divide down the voltage of your two outputs before they could be connected to any of our digital potentiometers. In addition, you need a comparator to actually detect the ripple, right? If you were planning to detect this with the potentiometer, please let me know by sharing a block diagram. Best, Katlynne Jones
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Forum Post: RE: DAC82001: Output noise (0.1 - 10Hz) graph
Hi Sato-san, I think Lucas is still waiting on a response. He will respond when he hears back. Best, Katlynne
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Forum Post: RE: DAC82001: Output noise (0.1 - 10Hz) graph
Hi Sato-san, It will take another day to get a definitive answer on the accuracy. I will reach out to you when I know more. Thanks, Lucas
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Forum Post: RE: ADS1220EVM: Can't Manually install the ADS1220EVM plugin in ADCpro
Hi Timo, I'll consult with the team what the issue might be and will get back to you soon. Best Regards, Angel
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Forum Post: RE: ADS1220: Measure of RTD Pt100 with ADS1220 and STM32H7 (over SPI connexion)
Hi Zabieru, Apologies for the late response. I will take a closer look at this issue and get back to you soon. Best Regards, Angel
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Forum Post: ADC12DJ5200RFEVM: Diagrams in ADCxxDJxx00RF Evaluation Module User's Guide
Part Number: ADC12DJ5200RFEVM Other Parts Discussed in Thread: LMK04828 , LMX2594 I have some questions about ADCxxDJxx00RF Evaluation Module User's Guide (Rev. B) User Guide URL: https://www.ti.com/jp/lit/ug/slau640b/slau640b.pdf?ts=1716456114996&ref_url=https%253A%252F%252Fwww.ti.com%252Ftool%252Fja-jp%252FADC12DJ5200RFEVM Q1. I consider that the SYNC signal input from the LMK04828 to the LMX2594 is used to align the output signals of multiple LMX2594 devices. (Fig7-2) In the EVM diagram, there is only one LMX2594, so there is no need to input the SYNC signal, right? Q2. When using the Onboard Clocking System(Fig 7-2), the SYNC signal and SYSREFREQ signal are input from LMK04828 to LMX2594. But, why are the SYNC and REFSYSREQ signals not input in the External Reference Clocking System(Fig 7-3)? Q3. Why does the origin of SYSREF change just by changing the input source? Q4. I believe that the LMX2594 outputs RFOUTA and RFOUTB need to be synchronized. The External Reference Clocking System is satisfied because RFOUTA and RFOUTB are generated from OSCIN. How does Onboard Clocking System synchronize? Q5. What is Board SYNC? Is it different from the SYNC~ sent from the RX side of JESD204?
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