Hi Raymond The DAC38RF82EVM and TSW14J56EVM can be configured for the 8 bit real data mode. There are some constraints related to your desired output signal that you should be aware of: The DAC outputs are converted to single ended using a balun transformer with an AC-coupled output. This may band limit the low frequency content of the output signal enough to prevent an accurate sawtooth from being created. Please refer to the DAC output circuit schematic in the DAC38RF8x EVM User Guide. ( http://www.ti.com/lit/pdf/slau671 ) The pattern must be a multiple of 256 samples. This could constrain the frequency of your sawtooth signal. Changing the sample clock rate will help give more flexibility. I hope this is helpful. Best regards, Jim B
↧
Forum Post: RE: DAC38RF82: Generating an ARB with DAC38RF82EVM and TSW14J56
↧
Forum Post: RE: PGA411Q1EVM: Why does PGA411-Q1 angle and velocity readout fail when FAULTRES is not kept LOW?
Markus, Thank you for the detailed notes. When the IZx pins are disconnected, it is normal for the angle output to continue changing. If you look at AOUT, you will see what looks like a constant velocity output. This will normally cause a fault when FAULTRES is high. LPEN and EXTEN cannot be used to enable the tracking loop/start the exciter when the device has detected a fault that turns off the exciter. Most of the fault status registers clear after reading, but this does not clear the fault state from the device. SFAULT reflects the state of the FAULT pin, so it will not be cleared until FAULTRES is toggled. A SPI fault will cause the FAULT pin to be triggered, but you should still be able to read angle and velocity data. Your description of "case 2 - with IZx connected" is still inconsistent. We should see a fault in one of the STAT registers when the fault pin goes high. Can you try timing how long it takes for the fault pin to be asserted after FAULTRES is brought high? You can check this by monitoring the FAULT pin. You can also monitor the AOUT pin and/or the OEx pins to see when the digital tracking loop and exciter output turn off. Thanks, -Clancy
↧
↧
Forum Post: RE: ADC12DJ3200EVM: PCB
Hi new2day We generally will use Rogers 4350B or Megtron 6 materials on our high speed board designs, but we don't mix the materials in the same board. The choice of which is uses can sometimes depend on material availability at the board vendors we work with. I have not investigated Megtron 7 yet. Best regards, Jim B
↧
Forum Post: RE: DIX4192: DIR block of DIX4192
Hi, Hasebe-san, The DIR of the DIX4192 is able to stream data on the audio serial ports with a sampling rate up to 216KHz, so 192KHz sample rate is supported. The sample rate of the serial port is determined by the frequency of the WCLK signal when the device is configured as slave. The audio serial ports are configured using control registers 0x03 through 0x06. Regards, -Diego Meléndez López Audio Applications Engineer
↧
Forum Post: RE: TVP5150AM1: How to setup 7.5IRE ?
Hi Max, As far as I can tell, toggling between 0x40 and 0x60 does not alter the pedestal bit, which is bit 6, but rather you are altering bit 5. In both of 0x40 and 0x60 the pedestal presence bit is set to 1. To toggle the bit off, you will have to switch between 0x60 and 0x20. Thanks, Chris
↧
↧
Forum Post: RE: DAC5573: Using DAC5573 with single power supply
This issue is solved. I misread the schematic. The voltage from DAC5573 output is correct. I read it at the output of op-amp by mistake. thank you
↧
Forum Post: RE: DAC38RF82: Generating an ARB with DAC38RF82EVM and TSW14J56
Hi Jim, Thank you for your reply. 1. Part of the reason for choosing the DAC38RF82 was the fact that it didn't have a built in balun. In the DAC38RF80 specs you can indeed see that it constraints the low frequency range quite a lot. The external TCM3-452X-1+ balun on the DAC38RF82EVM has a way broader and flatter frequency response. So I'm not that concerned about it. Concidering that 400MHz should be the lowest frequency in a 400MHz sawtooth. 2. As it is an ARB I can just repeat the pattern and so increase the patern size until it becomes a multiple 256. Say I repeat my 22 sample pattern 128 times. That will end up as 2816 sample pattern, which is an integer multiple of 256 (11). I'll look into changing the clock frequency, as long as it doesn't negativly influence the JESD204b data path. For me this is pretty much a gohead. So it's been very useful. Cheers! Raymond Vermeulen
↧
Forum Post: CCS/ADS1281EVM-PDK: How to reduce the noise?
Part Number: ADS1281EVM-PDK Tool/software: Code Composer Studio Hi, I use ADS1281EVM-PDK . The following figure is a test.(500 SPS) Upper is a shortcut between AINP and AINN. Lower is connecting with sensor. The scale of sensor reading is large than others, I can't see the peaks. But there are some peaks exist in upper figure.(I would like to know what it is) The peaks have reproducibility in channels. we do test in different environment(in lab and outside the building). For example, the peaks is different between different channels. (maybe 10hz and 12hz in channel 1 and 7hz, 9hz,15hz in channel 2) But always in same frequency(10hz and 12hz in channel 1 and 7hz, 9hz,15hz in channel 2) in many test. So, What those peaks are? From PCB board?
↧
Forum Post: RE: DIX4192: DIR block of DIX4192
Hello Diego-san, Thank you for your quick reply. I understand your comment. However, I have one more question. When switching the input of external WCLK in slave mode, I think that it is necessary to switch the then Mute the output input. Is this correct? Best Regards, Y.Hasebe
↧
↧
Forum Post: PCM2707C: Three questions about oscillator operation
Part Number: PCM2707C Dear Support team, Our customer will use PCM2707C in their application. Please tell me three questions about the oscillator circuit. Please refer to attached PDF file. Questions about oscillator operation Data Sheet In the equivalent circuit diagram of the oscillator shown in Figure 27, it can be understood that oscillation starts when power is supplied. However, when they check the waveform using the oscilloscope, oscillation will not start immediately even if VBUS supplies it, and oscillation will start from the bus reset state. Question-1 : Is this oscillation operation correct ? Question-2 : Immediately after power up, XTI and XTO both go high level. Is this correct ? Question-3 : When D + is open, oscillation started about 3 ms after power supply input. Is this correct ? Best Regards, Hiroaki Masumoto (Please visit the site to view this file)
↧
Forum Post: RE: TVP5150AM1: How to setup 7.5IRE ?
Hi Chris, Thank you! You are right! I made a big mistake.. The pedestal setting is bit 6 , it should be mask 0x40, not set 0x40. We set register 07H is 0x20 to check the black level of the NTSC-M and it is workable. Best regards, Max
↧
Forum Post: RE: TPL0401A-10-Q1: I2C interface no ACK response during device addressing
Thank you Uttam, The problem closed. The reason is simple: they connect SCL out of FPGA to SDA input of our device. Regards,
↧
Forum Post: RE: DAC5672: control question: Cannot make IOUT updated
Hi Neeraj, Problem still not fix. Customer shown the update waveform and they did 4 continuous clk pulses, do you think there is any other possibilities? Thanks!!
↧
↧
Forum Post: RE: ADS1220: TM4C129ENCPDT - SPI with ADS1220 register read back issue
Hi Bob, Thank you Sorry for the late reply, I have tried with the scope and as expected the data write to transmit buffer is happening in the following sequence " 0x07, 1 ms delay, 0x43, 0x01, 0xD4, 0x00, 0x00 1 ms delay 0x23 ". The SS pin at master and slave is permanently short to the same ground . while probing MISO of ADC, I am not receiving the expected register configuration sequence but some data is there, please find the same below. Am i right with the register concepts of ADS1220 ?. Please guide me to troubleshoot this issue. I am using a 100khz SCLK,
↧
Forum Post: ADS1118-Q1: ADS1118-Q1
Part Number: ADS1118-Q1 Hi, I am sending command to write config register and to read back config register data as well as to read conversion register. tx_data[2] = {0xC58B,0xC58B}; //single shot mode But i am receiving response back with correct config data and conversion data i am getting around 93 or 94 (adc count). This is not correct count as i need to get 2.5 volt correspondoing adc count (i am giving 2.5v between AIN0 and Gnd). What may be the issue please let me know. Thanks and Regards N sujendra
↧
Forum Post: RE: PCM1794A: Low frequency drift with static levels
They are pictures of the measurements we did on VOM, IREF and Vout (after the I2V AOP), PCM1794 input is a static value around full scale. Vout noise is following VCOM exactly.. Best regards
↧
Forum Post: RE: ADS1220: Problem in Thermocouple and RTD signal transmitter Design
Hi Bob, I will focus on the TC for now, my plan is to use isolated DC-DC converter to supply the ADC with unipolar supply(3.3V), and I will use two bias resistors to set the common-mode to mid AVDD. In this case the design should work with grounded and ungrounded TCs as well? Regarding TVS diodes I found one device with low current leakage and I am planning to use it (PTVS30VP1UP). Regards, Mahmoud
↧
↧
Forum Post: RE: Gerneral question about how to choose the right differential signal type for ADC
Hello Tom Thanks for your feedback. I think your point is the input range of the analog input. Nowadays, there is some micro with the embedded ADC which have the differential mode. I think to understand embedded ADC input type is important. Is it full differential or pseudo differential? Even in pseudo differential ADC, if the sampling frequency is much higher than the common mode noise frequency, it will also helps to reject common mode noise. Thanks!
↧
Forum Post: RE: DAC081C081: DAC081C081
you need source code?
↧
Forum Post: RE: DAC081C081: DAC081C081
Please send. Regards, Uttam
↧