Hi Fabrizio, Welcome to E2E and thank you for your query. Could you please recheck the slave address of ADS1015 ? Because there is a possibility that it may clash with the broadcast address of the DAC. I just want to make sure that is not the reason. Could you please also send a scope capture of the waveforms? Regards, Uttam Sahu Applications Engineer, Precision DACs
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Forum Post: RE: DAC081C081: DAC081C081
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Forum Post: About recommended products
Hi, Customers are looking for products that meet the following specifications. (looking for products as close as possible) ・Resolution Bit： over 8bit ・Sample/Update Rate：about 125MSPS ・Power Consumption： Low power as possible Product image is below. http://www.analog.com/en/products/digital-to-analog-converters/ad9714.html Could you tell me your recommended products? Best Regards, Yusuke/Japan Disty Power Consumption
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Forum Post: ADS8568: ADS8568 wake up issue
Part Number: ADS8568 Dear Team, My customer is having 2 ADS8568 chips on board on top and bottom on a few cm distance from their FPGA. They are reporting that once every few power ups the ADC is waking up in a state where it's internal Vref is very close to zero resulting wrong readouts. They are using the internal Vref. The phenomena is very hard to duplicate but is still occurring from time to time. The two ADCs are configured to the exact same configuration using the same commands. Even if the customer does not configure the ADC and work in the default mode - this phenomena still occurs. In addition the phenomena always occurring in the same (bottom) ADC. They have assembled 4 boards and the phenomena is consistent across all the four boards. Do you know of any such issue with the ADS8568 ? Can you help us debugging this ? Can this be occurred maybe due to slow/fast slew rates of the VCC ? Best regards, Nir
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Forum Post: RE: ADS1298: Address of Lead Off Status register
These are the snaps taken from a greater resolution with different logic analyzer.
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Forum Post: ADS124S08EVM: Delta Sigma EvaluaTIon Software: How to save data without Data analysis tab
Part Number: ADS124S08EVM Hello I'm collecting data from the ADS124S08EVM with the Delta Sigma EvaluaTIon Software. This works perfect for short measurement, unfortunately for overnight measurement with higher number of samples the software stops working when trying to open the data analysis tab. Is there another way to access and save the logged data? Can i collect data using another method? Thank you in advance and best regards Michael
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Forum Post: ADS1263EVM-PDK: ADS1263EVM
Part Number: ADS1263EVM-PDK Dear sir, This week I got the ADS126EVM-PDK evaluation module with MMB0 board. I am working on desktop PC under Window 7 professional OS installed. After the software installation, I clicked EVM and select the ADS126XEVM. Then after some processing I saw a massage “DSP not ready Retrying…”. After that massage I saw also “The firmware load has failed due to timeout condition. Please reset the H/W to continue loading the firmware” Pop-up. In this step, I also saw a “e” on display on the MMB0 board. I am sure all jumper on both board are properly set and the voltages 4 green LED were OK(Green color lights ON). After that did not process on the ADCPro screen anymore. I have retest it several times but have no change. Please help me, I attached the captured ADCPro screen. Best Regards, (Please visit the site to view this file)
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Forum Post: RE: ADS131E04: SPI Interface Initialization Problem
Hi Ryan, sorry for the long response delay. I solved the problem as follow: - START signal LOW - Sending SDATAC command before to send RREG or WREG registers - Changed CPOL and CPHA settings for the PIC32 (master) in : - DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_RISE - SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE Thank you for all the support given to me. Salvatore.
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Forum Post: Gerneral question about how to choose the right differential signal type for ADC
So far as I know, there are 2 kinds of differential signal. Pseudo-differential and full-differential. What will happen if I connect a full differetial signal to a pseudo differential ADC Or if I connect a pseudo differential signal to full differential ADC. Thanks!
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Forum Post: RE: PGA411Q1EVM: Why does PGA411-Q1 angle and velocity readout fail when FAULTRES is not kept LOW?
NCS is toggling between SPI frames. It is 600ns high before the next SPI frame. This should be ok according to the datasheet. What I additionally sometimes see is that the CS ans CLK lines partially toggle between SPI frames. This would explain, that the chip sees incomplete SPI frames and signals SPI error. GND connection is checked (impedance in mOhm, voltage between ground 1-2mV (tolerance of meas. device). The readout config I posted in Jun 23, 2017 7:10 AM is when I held FAULTRES LOW. Maybe I sum up here to not get confused, what I can currently observe: ----- with no connection on the IZ* and OE* pins ("open") ----- - case 1: "keep FAULTRES LOW:" if I do that, I do not read any faults (SFAULT via SPI). EXTEN=1 and LPEN=1 are kept (I just run this case again >5min). In this state I'm able to read angle/velocity values as expected, but are not reasonable as no IZ*, OE* connection. - case 2: "toggling FAULTRES once after config is verified (should be ok as the datasheet mentioned "deglitch" time; this is surely passed by then) and then keep FAULTRES HIGH until SFAULT detected:" I read SFAULT=1 in STAT4; when observed, I toggle FAULTRES (high-low-high, 100us in low). SFAULT is read as 0. But the exciter is disabled. Here I see FLOOPE=1, OMIZ1L=1 and OMIZ2L=1. Where I can confirm that OMIZ2L and OMIZ1L are set to 1 at the same fault. After some time, I only read SFAULT=1, but I see no change in STAT1 and STAT3; so I read error, toggle FAULTRES, but cannot say which error it is. When I reach this, EXTEN=0 an LPEN=0 and cannot be reactivated by writing to CONTROL3. ----- with connection on the IZ* and OE* pins ----- - case 1: as above, but angle/velocity values now make sense; EXTEN=1 and LPEN=1 are kept; (again tested >5min) - case 2: angle/velocity readout ok; but the case that EXTEN and LPEN are disabled (set to 0) occurs, but from STAT1, STAT3 (and STAT4) I cannot say which error it was; there is only SFAULT=1. And EXTEN and LPEN cannot be re-enabled once they come to 0. In both cases where the IZ* and OE* are connected I read the following config when EXTEN=0, LPEN=0: (STAT1 and STAT3 are only read after SFAULT=1 is read first, but SFAULT=1 stays at 1 at this state) ConfReg = ( DEV_OVUV_1 = (CRC = 60, ResStatus = 0, OSHORTH = 0, OSHORTL = 0, EXTILIMTH_H1_2 = 5, EXTILIMTH_L1_2 = 5, EXTOUT_GL = 8, ADDR = 83) DEV_OVUV_2 = (CRC = 40, ResStatus = 0, DVMSENL = 5, DVMSENH = 5, TRDHL = 3, XEXT_AMP = 0, res = 0, ADDR = 107) DEV_OVUV_3 = (CRC = 52, ResStatus = 0, OOPENTHH = 7, OOPENTHL = 7, OVIZH = 3, OVIZL = 0, EXTOVT = 7, EXTUVT = 7, ADDR = 101) DEV_OVUV_4 = (CRC = 11, ResStatus = 0, FSHORT_CFG = 1, nBOOST_FF = 1, VEXT_CFG = 0, AUTOPHASE_CFG = 0, TEXTMON = 7, TSHORT = 7, res = 0, ADDR = 236) DEV_OVUV_5 = (CRC = 53, ResStatus = 0, res = 0, TOPEN = 7, res2 = 0, ADDR = 82) DEV_OVUV_6 = (CRC = 61, ResStatus = 0, LPETHH = 3, LPETHL = 3, res = 0, BOOST_VEXT_MASK = 0, IZTHL = 7, res2 = 0, ADDR = 233) DEV_TLOOP_CFG = (CRC = 27, ResStatus = 0, DKI = 4, SENCLK = 0, OHYS = 1, DKP = 4, MKP = 2, res = 0, ADDR = 166) DEV_AFE_CFG = (CRC = 28, ResStatus = 0, GAINSIN = 1, GAINCOS = 1, res = 0, ADDR = 194) DEV_PHASE_CFG = (CRC = 36, ResStatus = 0, PHASEDEMOD = 0, EXTOUT = 0, EXTMODE = 1, APEN = 1, PDEN = 0, EXTUVF_CFG = 0, ADDR = 87) DEV_CONFIG1 = (CRC = 61, ResStatus = 0, MODEVEXT = 2, SELFEXT = 0, res = 0, NPLE = 0, res2 = 0, ADDR = 190) DEV_CONTROL1 = (CRC = 33, ResStatus = 0, DIAGEXIT = 0, MEXTMON = 0, MAFECAL = 0, MIZUV = 0, MIZOV = 0, MEXTUV = 0, MEXTOV = 0, MFLOOPE = 0, MFOCOSOPL = 0, MFOSINOPL = 0, MFOCOSOPH = 0, MFOSINOPH = 0, res = 0, MFOSHORT = 0, res2 = 0, ADDR = 144) DEV_CONTROL2 = (CRC = 59, ResStatus = 0, ENEXTUV = 1, ENEXTMON = 1, ENBISTF = 1, ENIOFAULT = 1, ENINFAULT = 1, RDC_DISABLE = 0, res = 0, LBIST_EN = 0, ABIST_EN = 0, ADDR = 99) StatReg = ( DEV_STAT1 = (CRC = 39, ResStatus = 0, FOSHORT = 0, FGOPEN = 0, STAT = 0, FOSINOPH = 0, FOCOSOPH = 0, FOSINOPL = 0, FOCOSOPL = 0, FLOOPE = 0, EXTOV = 0, EXTUV = 0, EXTILIM = 0, FTECRC = 0, FCECRC = 0, FRCRC = 0, FLOOP_CLAMP = 0, ADDR = 129) DEV_STAT2 = (CRC = 0, ResStatus = 0, SORD = 0, SPRD = 0, res = 0, ADDR = 0) DEV_STAT3 = (CRC = 16, ResStatus = 0, FIZH1 = 0, FIZH3 = 0, FIZH2 = 0, FIZH4 = 0, FIZL1 = 0, FIZL3 = 0, FIZL2 = 0, FIZL4 = 0, OMIZ1H = 0, OMIZ3H = 0, OMIZ2H = 0, OMIZ4H = 0, OMIZ1L = 0, OMIZ3L = 0, OMIZ2L = 0, OMIZ4L = 0, ADDR = 132) DEV_STAT4 = (CRC = 42, ResStatus = 0, SOUTZ = 0, SOUTB = 1, SOUTA = 1, SFAULT = 1, IOFAULT = 0, FVDDOV = 0, FVCCOV = 0, LBISTF = 0, ABISTF = 0, FEXTMODE = 0, FTSD2 = 0, FVDDOC = 0, FBSTOV = 0, SPI_ERR = 0, FEXTMONL = 0, FEXTMONH = 0, ADDR = 31) DEV_STAT5 = (CRC = 53, ResStatus = 0, ORDANGLE = 1, ORDCLOCK = 0, PRD = 1, res = 0, ADDR = 65) DEV_STAT6 = (CRC = 3, ResStatus = 0, ORDVELOCITY = 0, PRD = 0, res = 0, ADDR = 111) DEV_STAT7 = (CRC = 17, ResStatus = 0, REVID = 3, OPTID = 1, DEVSTATE = 1, FAFECAL = 0, res = 0, ADDR = 225) RwReg = ( DEV_CONTROL3 = (CRC = 40, ResStatus = 0, EXTEN = 0, LPEN = 0, SPIDIAG = 0, reserved = 0, ADDR = 221) DEV_CLCRC = (CRC = 55, ResStatus = 0, ECCRC = 0, res = 0, ADDR = 79) DEV_CRC = (CRC = 15, ResStatus = 0, RCRC = 97, res = 0, ADDR = 15) DEV_CRCCALC = (CRC = 4, ResStatus = 0, CRCCALC = 255, res = 0, ADDR = 217) DEV_EE_CTRL1 = (CRC = 24, ResStatus = 0, EECMD = 0, res = 0, ADDR = 227) DEV_CRC_CTRL1 = (CRC = 46, ResStatus = 0, CRCCTL = 0, res = 0, ADDR = 122) DEV_EE_CTRL4 = (CRC = 32, ResStatus = 0, EEUNLK = 0, reserved = 0, ADDR = 186) DEV_UNLK_CTRL1 = (CRC = 2, ResStatus = 0, DEVUNLK = 240, res = 0, ADDR = 100) For the short testing, I used case 2 with connected IZ*, OE*, and I see that FOSHORT=1 is set when COS or SIN pins are shorted (IZ* shorted), and is cleared when short is removed. BR, Markus
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Forum Post: ADS7042: ADS7042
Part Number: ADS7042 I am trying to calculate the maximum sampling rate for ADS 7042 ADC. But from the data sheet if I calculate the time I am getting only 996.5ns (1/ (12.5 * 62.5 + 15 + 200 )) for one sample. This will be greater than the sampling rate specified in the timing diagram. I am unable to predict where my calculation went wrong Can anyone figure out that. Also, the acquisition time is not getting added up to 200ns if I calculate individually from the datasheet.
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Forum Post: ADS1262: Data rate
Part Number: ADS1262 Hi all, I am testing a new design with ADS1262 and cannot make it to run at fast sampling rate. Running scenario: 1. Do set-up for the ADC via SPI. Read the value at beginning, then reconfigure and write data back to the ADS1262 . Read again to make sure registers are set correctly. Set-up details is listed below. 2. Enable a timer interrupt on MCU, aiming at 20kHz (the device specification says it can do more than 38kHz) 3. At timer interrupt, pull START pin up to trigger a conversion 4. #DRDY pin is connected to an Interrupt pin on MCU. When #DRDY triggers, the MCU interrupt immediately read the ADS1262 , and pull the START pin to low. The sequence repeats with timer interrupt and #DRDY interrupt. Problems: The time for #DRDY to go low from START signal is measured at about 208us. This is too slow and not correct according to the datasheet. Please see the attach photo Below are the settings that I tried: config->internal_ref_en = 1; //enable internal reference config->crc_en = 1; //enable crc byte config->status_en = 1; //enable status byte config->chop = 0; //disable chop config->delay_idx = (((uint8_T)0U)); //no delay - default config->pulse_mode_en = (((uint8_T)1U)); //enable pulse mode conversion config->filter_idx = (((uint8_T)0U)); //filter selection set to 0: sinc1 filter config->pga_bypass = (((uint8_T)0U)); // enable PGA config->pga_gain = (((uint8_T)5U)); // pga gain set to 0x5 (0101b): 32V/V gain config->datarate_idx = (((uint8_T)15U)); // DR set t0 0xF : 38400 SPS config->neg_input_mux = (((uint8_T)2U)); // Negative input: AIN2 config->pos_input_mux = (((uint8_T)0U)); // Positive input: AIN0 config->neg_ref_mux = (((uint8_T)3U)); //Negative Reference input: AIN5 config->pos_ref_mux = (((uint8_T)3U)); //Positive Reference input: AIN4 All other values are kept as default. I'm not sure what I have done wrongly. Any help is much appreciated. Many thanks, Phil
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Forum Post: connectors in Body Weight Scale Reference Design
Hello, I want to know the purpose of connectors (CR0 to CR11) used with the AFE4300 in the Body Weight Scale Reference Design with Body Composition capability and BLE Connectivity( TIDA00009).
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Forum Post: RE: PGA450Q1EVM: I had programmed the PGA450EVM-S using the GUI .Now i want to use it into an application where it needs to be interfaced with to msp430 and programmed using the energia.
Hi sir, According to my project , i am supposed to use only the ti micro controller.I had ordered some local ttl converter as of now as i am in urgency in getting the output. Meanwhile in order to save time,i decided to verify the software and i was confident as you said my code was almost right. i interfaced the tida sensor with the arduino mega uart 1.I then uploaded the following code:- void setup() { Serial1.begin(19200); Serial.begin(9600); } void loop() { int sensor1; byte message[] = {0x00,0x55,0x11,0x02,0x00 }; Serial1.write(message, sizeof(message)); sensor1=Serial1.read(); Serial.print(sensor1); Serial.println(); delay(1000); } The following was my observation in the serial monitor:- Whether the sensor is given power or not and whether connected to the arduino mega or not ,it gives some reading and is obviously not hexa decimal values. Also i must mention this,even when the sensor was interfaced with the tiva c series launchpad,i received the same values. Some of the readings which i get are 17 26 2 0 255 and some more random values being repeated. I don't understand where the values come from. I feel that the uart is not connected but i connected the tx and rx pins of the sensor along with the rx and tx pins of the arduino mega. Previously you said that i was not getting the output as the logic levels are in 3.3v and it is supposed to be in 5 v .But i had connected it with arduino mega which has 5 v ttl logic .But still i am not able to get the output .As you said the logic level was an issue .But now ,that got rectified .You also verified my code . Now both software and hardware is right as per your answers,but still i am not able to get the answers, Is there any possibilities that i might have gone wrong ....if there might be any ,kindly help me in identifying that and get rid of this problem. Thanking you Regards Hariram Rajagopalan
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Forum Post: RE: DAC081C081: DAC081C081
Hi recheked slade ID od ADC (0x49)and not is bloardcast address of DAC ( it is 0x48). Now i can't send waveform, if you want can send source code use for read and write on ADC and DAC. Fabrizio
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Forum Post: RE: TLV320AIC3104: deactivating AIC3104 connected to cc8520
Hi, Roger, The TLV320AIC3104 can be powered down or placed in a standby mode. You would need to disable the ADC and DAC blocks of the TLV320AIC3104 . In order to make this, you would need to configure the page 0 / registers 19 , 22 and 37 in reset value. Best regards, Luis Fernando Rodríguez S.
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Forum Post: RE: PCM1794A: Low frequency drift with static levels
Hi Diego, I am glad to hear you again. As you can see, we continue to investigate around VCOM as it looks to be the cause (or the image) of the noise we observe, please see the picture, this is the ouput of the I2V converter stage, after Iout. p-p variation is 5.6mV, although DAC input is steady. Second picture is VCOM noise. How VCOM is generated internally, any schematic or detail will help. Best regards. Daniel
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Forum Post: RE: ADS1262: Data rate
Hi Phil, This this a delta-sigma ADC with a low-latency digital filter. Even though it is low latency, there is still some delay between the start of a conversion and when /DRDY goes low. In the case of the 38.4 kSPS, the digital filter is a SINC5 filter, which takes roughly 5 conversion periods to get the first conversion result (think of a moving average filter that is averaging 5 results). This is known as the conversion latency, as is given for each data rate and filter type in table 17: You're measuring the 38.4 kSPS, SINC5 filter conversion delay precisely. Please note that is delay only applies to the fist conversion result, every consecutive conversion result will appear at regular intervals of the data rate period. For conversion latencies that only require about 1 conversion period to settle, you would need to use either the SINC1 or FIR filter at one of their supported data dates. To learn more about these filters and the latency associated with them, refer to the following application note: Best regards, Chris
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Forum Post: RE: ADS7042: ADS7042
Hello Chaitanya, The maximum sample rate for the ADS7042 is 1 MSPS. To sample at 1 MSPS the SCLK frequency must be set to 16 MHz. I have gone through the math similarly to how I presume you did and I understand your confusion since the timing diagram shows an acquisition time that can be less (if using all minimum specifications) than the 200 ns that the datasheet defines. In order to ensure proper operation and performance, the ADS7042 should be operated at a maximum sample rate of 1 MSPS. Below I have worked through the equations to find the minimum cycle time. The result is a minimum of 996.25 ns (equivalently 1.0037 MSPS). Since all of the timing specifications were minimum requirements, operating at 1 MSPS is very close to the obtained result. I hope this helps answer your question. Please reach out if you have any further questions. Thank you, Reed Kaczmarek
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Forum Post: RE: ADS1263EVM-PDK: ADS1263EVM
Hi Jenny, Most likely this is related to a driver installation problem. Please see this related E2E thread: e2e.ti.com/.../1749129 Best regards, Chris
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Forum Post: RE: ADS1262: Data rate
Hi Chris, Many thanks for your response. In your answer, you mentioned: [quote user="Christopher Hall"] Please note that is delay only applies to the fist conversion result, every consecutive conversion result will appear at regular intervals of the data rate period. For conversion latencies that only require about 1 conversion period to settle, you would need to use either the SINC1 or FIR filter at one of their supported data dates. [/quote] My question would be how to get the consecutive conversion result? I have the second stage filter set to SINC1 as your suggestion, but it seems that the conversion delay is consistent at 208us. Please see the photo below. Kind regards, Phil
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