Forum Post: RE: DAC38J84: 4 independent outputs
Yes it does. The SERDES rate is 9600Mbps, which is supported by TSW14J56. The DDR of the J56 is 2G-samples, and it should be plenty to support all four channels. -kang
View ArticleForum Post: RE: ADC084S021: ADC084S021 example code
Hello, Unfortunately we do not have an example code for this device. I would suggest following the timing diagram provided in the datasheet, and confirming it is correct by using an oscilloscope on the...
View ArticleForum Post: RE: ADS8638: data invalid for first couple of reads, then OK
Hi Nick, Understood, thanks for explanation. Can you please confirm how many cycles you got 0 hex code (ADC ADDRESS = 0 hex ADC DATA = 0 hex)? two cycle 0 hex data are reasonable because each DIN...
View ArticleForum Post: RE: ADC12D1800: Recommended power-up sequence for NON-DES mode...
Hello Itay I have copied your comments and questions here along with my responses: We set the NDM bit to logic low '0' - DEMUX mode (i.e. We use both DI and DID for sampling the I channel). About the...
View ArticleForum Post: RE: ADS1602: Harmonic at low frequency
Hello, I have not been able to find any data at 20Hz up to this point. I still have more data to go through, and if I find anything, I will provide an update. Regards, Keith
View ArticleForum Post: RE: ADS131E08EVM-PDK: Not able to see correct ADC input on...
Tejaswini, I don't see anything in the setup that looks unusual, so I'm not sure what is wrong yet. The test signal also looks similar to Figure 16 of the ADS131E08EVM user's guide. Have you looked at...
View ArticleForum Post: ADS7049-Q1: SCLK input timing requirement
Part Number: ADS7049-Q1 Hello team, I have a couple of questions about external SCLK input for ADS7049-Q1 . The tPH(PL)_CK is required 0.45~0.55tSCLK duty cycle in the Timing Requirements. 1) Is this...
View ArticleForum Post: RE: ADS1602: Harmonic at low frequency
Hello Thank you for your comment. I am designing a lock-in amplifier with ADS 1602. Line noise is avoided. It was improved by changing the capacitor 10 uF to 1000 uF in Figure 43. We expect the...
View ArticleForum Post: RE: DAC9881: Power-Supply Sequence
Duke-san, Thank you for your detailed explanation. POR and hardware reset are same behavior, aren't they? Best regards, itabi
View ArticleForum Post: DAC39J84EVM: Missing EVM GUI software for DAC3xJ8xEVM
Part Number: DAC39J84EVM The user manual for DAC39J84EVM (SLAU547B) states that a zip file for the GUI s/w is available on the product page ( www.ti.com/.../DAC39J84EVM). "The software can be...
View ArticleForum Post: RE: ADC32RF45: Load/Store Offset Corrector Coefficients
Hi Ozer, It should be possible to do factory calibration as you described. I'm checking with the design team for the procedure to read and write the offset corrector coefficients. I will verify it on...
View ArticleForum Post: RE: ADS131A04EVM: ADS131A04EVM
Hi Joseph, For the noise i have next results: Settings Board: bipolar supplies (JP11 2-3), internal reference enable (JP9 OFF and software enable), Script: Basic startup with Datarate @ 8kSPS 1)...
View ArticleForum Post: RE: DAC39J84EVM: Missing EVM GUI software for DAC3xJ8xEVM
Hi Bill I have notified the DAC39J84EVM expert regarding this issue. He will look into the issue and respond as soon as possible. Best regards, Jim B
View ArticleForum Post: ADS7953: Misssing Codes
Part Number: ADS7953 Hi Team, I'm using an ADS7953SRHBT in this design. In general, the results are correct for every converted channel, it's just that the ADC seems to get stuck on certian codes. The...
View ArticleForum Post: ADS1218: DYDY related issue.
Part Number: ADS1218 Hi All, IN ADS1218 , user is suppose to read the data when DRDY goes low. Is it mandatory to read this data in every DRDY low cycle? Let us say I read the data after few DRDY...
View ArticleForum Post: ADS1256: Power Drain during channel switching
Part Number: ADS1256 Hi, This is in regards with ADS1256 . History: The ADS1256 VDD is connected to 3.3VDC rather than 5VDC, this is an design error. Since we did not notice any abnormal operation on...
View ArticleForum Post: RE: Compiler/ADS1298ECGFE-PDK: FFT results not matching with...
Hi ryan, We have used the high impedance termination to source end, we have used two inputs 20mVpp and 50mVpp(to channel 2) and given a supply of 6VDC for the card and this is following result...
View ArticleForum Post: PADC12DJ4000RFAAV : JESD204B Link up failure for Sampling Rate of...
Hi, We are using ADC : PADC12DJ4000RFAAV in our design in JMODE3. We have tested it with the sampling rate of both 4GSPS and 3.2GSPS. It is working fine at both the frequencies. But JESD204B Link up is...
View ArticleForum Post: RE: ADC12DJ3200EVM: ADC12DJ3200EVM
Hi In regards to Eli's question I have another one If and when the firmware package will be available ( for the ADC12DL3200EVM and the TSW14DL3200EVM FPGA platform ) Will you release also the Firmware...
View ArticleForum Post: AFE5818EVM: connect with TSW1405 for simultaneous 8 channel...
Part Number: AFE5818EVM 1). Can we connect AFE5818EVM with TSW1405 capture card for simultaneously 8 channel data capture? 2). Can we connect AFE5818EVM with TSW1250 capture card for single channel...
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