Forum Post: RE: GUI 1.0.3.0, I doubt Indactance value
Dear Ben Kasemsadeh,thanks for your reply.Of course, I set "Sensor Capacitor Value".I set the parameter as below; Rp MAX: 349,066Ω(349.066k) Rp MIN: 38,785Ω (38.785k) Raw: about 26300 Fext: 8MHz...
View ArticleForum Post: RE: Problems about the coil design of LDC1000
Hi, SunnyThank you so much for your answer. And I want to ask you that whether your result of the value arrange come from an actual test. Can I get some theory to support them?Thanks for your...
View ArticleForum Post: RE: PCM1863 datasheet issue
Hi, Ward,Thanks for bringing this issue to our attention. You are correct that Figure 2 is correct, and Table 1 is not. We will get the data sheet updated, thanks for your information.-d2
View ArticleForum Post: RE: LM49350 PCB Design Guidelines
Hi, Juan,Page 96 onwards in the d/s shows the schematic and layout for a demo board we made when this product first came out (unfortunately, they are no longer available). Suggest you refer to that...
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Forum Post: DAC38J84 / About IOUT_FS
Hi,Our costomer have evaluated DAC38J84EVM/revision-D.The results were different from work out on paper.◆work out on papercoarse_dac=10[dec],V_EXTIO=0.9[V],R_BIAS=1.91[kΩ]The data sheet says that...
View ArticleForum Post: RE: TSW1400 EVM capture event and USER_LED interpretation
Jim,There is no issue with the board I need this information for my custom algorithm on PC.Let me rephrase the question.1.What is the estimated time when the following command is issued on PC to when...
View ArticleForum Post: RE: Lmp90079 strange behavior
Hi Paolo,You can set the LMP90079 to stand-by by writing to register 0x08, then program the registers as required, set the LMP90079 to active mode with register 0x08 and then start conversion with...
View ArticleForum Post: TLV320ADC3101 PLL jitter
I have a design where I have a low frequency MCLK (812 kHz) with some phase jitter. The PLL then produces all clock signals for 48 kHz sample rate. There is noise in digital output that depends very...
View ArticleForum Post: RE: DAC38J84 and JESD204B latency calculation
Hi Rick,Sorry for the long delay, trying to get you the right information here. For 442 mode, the latency numbers are below. This is from the output of the JESD elastic buffer to the output of the DAC....
View ArticleForum Post: RE: PCM9211 ADC phase
Yes, the input buffers to the ADC are inverting. You can use Register ADPHASE to invert the ADC output phase. The digital filters will also affect the phase response.
View ArticleForum Post: RE: PCM1789 DAC LPF Design
Hi Don,I've surveyed the range of options. I do like the simplicity of the PCM5102 but in my application I need programmable digital gain. Looked like the PCM1789 was my best bet.Any thoughts on the...
View ArticleForum Post: RE: ADS1258 Idle Mode Question on How to Enter Sleep Mode
Hi Chris,Thanks! Great Answer. Yes, I am using the pulse convert command. As part of my initialization process I send the CONFIG registers and then read them all back to make sure they match. If...
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Forum Post: RE: ADCPro Can't Connect to ADS8881EVM-PDK
Hi Jason,During software installation, it is possible for windows to block driver installation depending on user privileges and/or too restrictive configuration settlings.Try installing the mmb0 driver...
View ArticleForum Post: RE: Question about the ADC12D800RF Reference board:the...
Hello Tianyi,The ADC12D800RFRB3 uses the same schematics and layouts as the design package above. Thank you for pointing out the absence of FPGA source code, which I have attached below:(Please visit...
View ArticleForum Post: RE: TLV320AIC3110
Hi,Eli,I tested on EVM:When SPLVDD=SPRVDD=5V,R=8ohms+33UH load,output power=1W/ch, the current of SPLVDD and SPRVDD=0.548A.Please let me know if you have some questions.Thanks,Flora Wang
View ArticleForum Post: RE: TSW1400EVM Trigger Issue
Thayne,I have never had an issue with R/F times. What is the original trigger generator? Perhaps the edge is so fast that it is ringing and then double triggering?Thanks,Chuck
View ArticleForum Post: RE: LDC1000 GUI Shows averaging
Hello Frank,please use the "Log Data" button in the bottom left corner to record individual samples.
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Forum Post: RE: ADS8881 / Daisy-Chain mode with a Busy Indicator
Hi Kato-san,The timing diagram below compares CPOL=1&CPHA=1 against CPOL=1&CPHA=0 to illustrate the details that allow 18*N. Note that to give SCLK margin, we recommend SCLK ≤ 36MHz for...
View ArticleForum Post: RE: TSW1400 EVM capture event and USER_LED interpretation
Venky,Please send me your email address and I will pass it on to a group that can possibly help you with this question.RegardsJim,
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