Part Number: ADC3563 Tool/software: Hi, I want to receive samples from the ADC3563 using an Intel Cyclone 10 LP FPGA. The Quartus design suite only offers an LVDS RX IP with data and clock inputs — there is no option for an additional frame clock (FCLK) input. My plan is to generate DCLK from the same SI5392 clock generator that also provides the ADC sampling clock (CLK). I would set DCLK to be exactly synchronous to CLK and the internal ADC decimation factor, such that the decimated output sample rate times the data width matches DCLK. In 2-wire mode (16-bit words), I would set: DCLK=Fsdec×8DCLK = Fs_{dec} \times 8 D C L K = F s d ec × 8 My idea is to connect only DCLK and the data lanes to the FPGA's LVDS RX IPs and use the ADC's built-in test pattern mode plus bit-slipping on the FPGA side to establish frame alignment during initialization. Once aligned, I'd switch the ADC back to normal sample mode. My question: Is this approach valid with the ADC3563? Specifically, will word framing remain stable when switching from test pattern mode back to normal sampling? Or is there any chance that alignment could be lost when changing modes? The motivation for this setup is that the Intel Cyclone 10 LP SERDES hardware and Quartus LVDS IP do not support an external FCLK input. Capturing FCLK in the FPGA fabric clock domain instead of the ADC clock domain seems pointless and error-prone, so I would like to avoid routing FCLK entirely if DCLK can be precisely matched to the decimated output rate. Thanks, Maik
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