Hi,
In single-bus interleaved mode, only A-channel input is used. B-channel can be left floating and “MODE” input pin has to be connected to DGND. CLKA (Pin 18) & WRTA (Pin 17) are shared for both of channels. In dual-bus mode, MODE has to be connected to DVDD and those two channels are running independently with two independent clocks.
A1] CLKDACIQ is disabled (low) when RESETIQ is high, which means internal sampling clock is set to low all the way till RESETIQ is low. There would be just random noise out of DAC without sampling.
A2] Yes, it is correct.
A3] I’ll update you soon.
A4] The SFDR performance for the channels will have some variation. We do not guarantee that these channels will match exactly, there will be some part to part and channel to channel variations. The only guarantee in the data sheet is a min SFDR @ 20MHz, 200Msps, even then it Is not guaranteed to match - other SFDR values are typicals. As long as the clock meets VIH, VIL and the setup and hold times (tsu, and th), then there should be no issues. If you feel your clock has excessive jitter then this may translate to your DAC output - clock jitter typically does not affect the spurious performance of the DAC. However if you have non-clock related spurs in your clock source these will show up in your DAC output and impact the SFDR performance.
A5] It depends on digital data path. If you want I/Q swap, you can set RESETIQ low when SELECTIQ is high.
A6] The clock latency from WRT to output is 4 clock cycles regardless of clock frequency.
Thanks,
KW
