Hello Keith, Thank you for your reply. I have checked voltage@ pin4 3V5 DC and pin 5 2V5 DC, I was using DMM, also board GND is connected to GND of the power supply. Still getting similar plot, please see bellow. I am thinking: would it makes sense to extend time between CS filing edge and first rising edge of SCK, add like half cycle SCK delay between? Please advise at your earliest convenience Thank you, Iouri
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