Dear Alexander, Even if I keep CLK low during power up it did not help. Sometimes the first clock from Diif.line.driver SN65C1167E seems not to keep duty cycle 50%/50% but starts at 38%/62% duty cycle and after few clock it stabilize to 48%/52% but looks like it do something to ADC and ADC then sending data with offset. I think I need to some impedance trace adjustment. Because One diff. line driver output feed four ADCs with clock on one trace. Do you suggest to have for every ADC some own clock driver and trace? Could it be something with the impedance trace adjustment with bad reflection? Kind regards Thomas
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