Hi. Wow that was fast. My hardware engineer looked at the graphs and agreed with you that the clock edge seems to be out of phase. I can reverse the polarity of the clock easily in the Xilinx SPI bus settings so I will try that right away. I will also pull the START high and do nothing else on the buss and see if the logic an. shows the 50 Hz. This is easy so I will get back in a couple hours with the data.
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