Hi Sachin, After browsing more information, I have thought more about this issue, before I said that the statement that the two AFE58JD48 are considered as a 32-ch/8-lane JESD transmitter should be wrong, these two AFE58JD48 (80x mode) should be received as four 8-ch/2-lane JESD transmitters. I still think I can use a Xilinx JESD204C IP core to handle these four JESD links, and only need to configure L/M/F=2/8/8 (80X) as per the AFE58JD48 documentation, since the JESD IP core maintains the rx ila data for each lane individually, is this right? Also, I have a question about your official AFE58JD48 JESD reference design, why only two lanes of the JESD rx core are activated in the code, when it is clear that in 40X mode (F=4) all lanes should be activated. Code location: JESD_TOP.v line34 parameter active_lanes = 72
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